Flash Memory Row Decoder Timing for Boost Leakage Suppression
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Solution Overview
Problem
The challenge of boost leakage in flash memory devices, which leads to unintentional data damage in inhibit strings due to charge leakage in memory cells, compromising data reliability as the channel voltage is unintentionally decreased.
Innovation Solution
Implementing a boost retention logic (BRL) in the row decoder to minimize boost leakage by controlling the voltage levels of non-memory transistor control lines, specifically reducing the voltage of victim non-memory transistor control lines to ground voltage during programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-boosting scheme is applied to inhibit string to prevent threshold voltage change, then program inhibition is improved, but boost leakage occurs causing charge leakage and data damage
Solution Approach 1:
The patent applies preliminary anti-action by applying a negative voltage to the control gate of the string selection transistor in the inhibit string before and during the programming operation. This negative voltage counteracts the self-boosting effect that would otherwise cause charge leakage in the channel, thereby preventing boost leakage while maintaining program inhibition reliability.
Solution Approach 2:
The patent changes the voltage parameter of the string selection transistor control gate from a typical high voltage (for turning on) to a negative voltage (for preventing charge leakage). This parameter change transforms the transistor into a blocking state that prevents charge leakage while allowing the self-boosting scheme to maintain program inhibition.
2Reliability
If channel voltage is boosted in inhibit string, then program inhibition is maintained, but charge leakage occurs causing unintended programming
Solution Approach 1:
The negative voltage applied to the string selection transistor control gate acts as a preliminary protective measure that prevents charge leakage before it can occur. This preliminary anti-action ensures that the channel remains blocked, preventing both boost leakage and unintended programming while maintaining data integrity in the inhibit string.
3Object-generated harmful factors
If string selection transistor is turned off to prevent charge leakage, then boost leakage is reduced, but channel voltage cannot be boosted for program inhibition
Solution Approach 1:
The patent merges two functions into the string selection transistor: (1) the traditional function of selecting and enabling memory strings for programming, and (2) the additional function of blocking charge leakage in inhibit strings by applying negative voltage. This merging allows the transistor to simultaneously maintain program inhibition capability while preventing boost leakage.
Solution Approach 2:
The string selection transistor is given multi-functionality by enabling it to operate in two distinct modes: (a) normal operation mode where it enables programming by turning on, and (b) inhibition mode where it prevents charge leakage by turning off with negative voltage. This universality resolves the contradiction by allowing the same component to serve both purposes under different voltage conditions.
Data Source
AI summary
The present disclosure relates to nonvolatile memory devices. An example nonvolatile memory device comprises a first string and a row decoder. The first string includes a plurality of memory transistors, a first non-memory transistor and a second non-memory transistor. The row decoder is configured to control a plurality of word lines respectively connected to the plurality of memory transistors, and first and second non-memory transistor control lines respectively connected to the first and second non-memory transistors. The row decoder is configured to decrease a voltage level of the first non-memory transistor control line at a first time point within a first time period during which a program voltage is provided to a word line of the plurality of word lines, and to decrease a voltage level of the second non-memory transistor control line at a second time point within the first time period.