Flash Memory Sensing Circuit with Modulated Clock and Successive Latching
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Solution Overview
Problem
Existing methods for programming and verifying multi-level cells in flash memory arrays face performance bottlenecks due to redundant sensing operations as arrays become more complex and smaller in size, necessitating an efficient method to improve programming performance.
Innovation Solution
An improved sensing scheme using a modulating clock signal and successive latching operations to eliminate setup time between sensing operations, allowing for more efficient verification of programming states in multi-level cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If redundant sensing operations are used for programming and verification in multi-level cells, then measurement precision is improved, but productivity deteriorates due to performance bottlenecks
Solution Approach 1:
The patent combines multiple sensing operations into a single unified sensing process. The sense amplifier performs multiple latching operations (first latch and second latch) without requiring intermediate setup time, merging what would traditionally be separate sensing steps into one continuous operation, thereby improving productivity while maintaining measurement precision
Solution Approach 2:
The sense amplifier is pre-configured with multiple latching capabilities before the sensing operation begins. The circuit is prepared to perform sequential latching operations without requiring external intervention or setup time between operations, enabling faster programming verification
2Volume of moving object
If memory arrays are scaled down in size to increase capacity, then volume is reduced, but device complexity increases due to more complex sensing requirements
Solution Approach 1:
The sense amplifier is designed as a universal circuit capable of performing multiple functions: it can latch threshold voltages at different reference voltage levels, perform both first and second latching operations, and handle verification for multiple memory cells simultaneously. This multi-functional design reduces the need for separate dedicated circuits for each sensing task, thereby reducing device complexity despite increased array capacity
Solution Approach 2:
The sensing circuit employs dynamic reference voltage switching, where the sense amplifier can dynamically adjust between different reference voltage levels (first reference voltage and second reference voltage) during the sensing operation. This dynamic capability allows the circuit to handle complex multi-level cell verification without requiring additional static circuitry
3Measurement precision
If setup time is included between successive sensing operations, then measurement precision is maintained, but loss of time increases due to overhead
Solution Approach 1:
The sense amplifier performs continuous latching operations without interruption or setup time between the first latch and second latch. The circuit maintains its sensing state continuously, transitioning directly from one latching operation to the next, thereby eliminating the time loss associated with setup operations while maintaining measurement precision through the sequential latching mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming performance by reducing overhead and improving the efficiency of programming and verification operations in multi-level cells, addressing the challenges of scaling performance with decreasing array sizes.
Implementation Method 1
The improved sensing uses a modulating clock signal and successive latching operations to eliminating overhead-inducing setup time between successive sensing
Implementation Method 2
The sensing operation includes latching the sensing output to a first level, and then latching the sensing output to a second level
Data Source
AI summary
A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.