Flash Wafer Shallow Trench Height Adjustment
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Solution Overview
Problem
In flash memory devices, the height difference between the polysilicon layer on the active area and the shallow trench isolation (STI) in the capacitance area, due to the absence of a floating gate, narrows the process window for etching and affects the thickness of subsequent film layers, making it difficult to control the etching procedure effectively.
Innovation Solution
A manufacturing method for a Flash wafer that adjusts the height of the silicon oxide filled shallow trench in the capacitance area without adding new masks, using a silicon nitride and silicon oxide layer as protection to maintain the height of the silicon oxide filled shallow trench in the cell area, allowing individual adjustments to the capacitance and logical areas while ensuring the silicon oxide filled shallow trench in the capacitance area is closer to the floating gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the height of the silicon oxide filled shallow trench in the capacitance area is increased to reduce the height difference with the floating gate, then the process window for etching is improved, but the height of the silicon oxide filled shallow trench in the cell area is also increased which weakens the coupling rate between the control gate and floating gate
Solution Approach 1:
The patent applies local quality by performing selective etching on the silicon oxide filled shallow trench in different areas. Specifically, the capacitance area undergoes etching to increase its trench height and reduce the height difference with the floating gate, while the cell area is protected from etching to maintain its original trench height and preserve the coupling rate. This localized treatment resolves the contradiction by applying different processes to different regions of the wafer.
Solution Approach 2:
The patent segments the wafer into distinct processing zones using masks. The capacitance area is exposed for etching while the cell area is protected, allowing independent height adjustment of the silicon oxide filled shallow trench in each region. This segmentation enables the capacitance area to have enhanced etching process window while the cell area maintains its original characteristics for optimal coupling rate.
2Manufacturing precision
If masks are added to adjust the height of the silicon oxide filled shallow trench in the capacitance area, then the height difference is reduced, but the device complexity increases
Solution Approach 1:
The patent merges the height adjustment process for the silicon oxide filled shallow trench with existing etching processes in the fabrication sequence. By integrating the selective etching step into the established process flow and utilizing existing mask structures, the patent achieves precise height control without requiring additional dedicated masks or process steps, thereby reducing device complexity while maintaining manufacturing precision.
Data Source
AI summary
A manufacturing method of a Flash wafer, comprises: fabricating a Flash wafer containing a cell area, a logical area and a capacitance area; adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area; sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area; adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area; depositing an interlayer dielectric layer on the surface of the Flash wafer; removing the rest part in the logical area by protecting the cell area and the capacitance area with a mask.