Flash Memory Word Line Height Optimization
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Solution Overview
Problem
In flash memory devices, the concave shape of word lines with heights greater than erase gates complicates contact formation and leads to insulation issues due to increased aspect ratios, resulting in void defects and humps between adjacent memory cells, which hinder reliable read/write operations.
Innovation Solution
The flash memory device features a word line with a height that monotonically increases from the outer side to the inner side, reducing the height at the outer side to be smaller than the erase gate height, eliminating 'pulled-up' edges and improving contact resistance, thereby facilitating better filling of the dielectric layer and enhancing operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line height is increased to be greater than the erase gate height, then the word line can provide better electrical isolation, but it creates concave shapes that complicate contact formation and lead to void defects
Solution Approach 1:
The patent changes the height parameter of the word line from being greater than the erase gate height to being substantially equal to or less than the erase gate height. This parameter change eliminates the concave shape formation while maintaining adequate electrical isolation through alternative design configurations, thereby resolving the contradiction between electrical isolation and contact formation quality.
2Reliability
If the word line height is increased, then the word line can achieve better signal shielding, but it increases the aspect ratio leading to insulation issues and hump defects between adjacent cells
Solution Approach 1:
The patent modifies the word line height parameter to be substantially equal to or less than the erase gate height, which reduces the aspect ratio and eliminates hump defects between adjacent memory cells. Signal shielding is maintained through proper spacing and grounding configurations rather than relying on increased height, thus resolving the contradiction between signal shielding and device complexity.
3Manufacturing precision
If the word line height is reduced to be smaller than the erase gate height, then contact formation is simplified and void defects are eliminated, but the word line may have reduced electrical performance
Solution Approach 1:
The patent optimizes the word line height parameter to be substantially equal to or less than the erase gate height, achieving improved contact formation and elimination of void defects. Electrical performance is maintained through compensating design elements such as optimized word line thickness, material selection, and interconnect configuration, thus resolving the contradiction between manufacturing precision and electrical performance.
Data Source
AI summary
The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.