Flexible Contactless Wire Bonding for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor device manufacturing processes, particularly for field-effect transistors, face challenges in minimizing wire interconnect resistance and eliminating the destructive welding process used to connect bond wires to the source electrode, which limits the reduction of composite resistance and affects device performance.
Innovation Solution
The implementation of a leadframe structure with electrically isolated leads and a semiconductor die, where copper wires are bonded to an aluminized source electrode coated with a thin solderable material, allowing for reflow and solidification of solder to create a low-resistance conductive medium between the leads and the source electrode, reducing composite resistance and eliminating the need for welding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If welding process is used to connect bond wires to source electrode, then electrical connection is established, but composite resistance cannot be minimized and device yield is reduced
Solution Approach 1:
The patent extracts and eliminates the welding process from the bond wire connection method. Instead of welding copper wires to the aluminum source electrode, the invention uses a separate solder layer that is applied to the source electrode surface, allowing wires to be connected without direct welding, thereby improving yield while achieving low resistance.
Solution Approach 2:
The patent introduces a solder layer as an intermediary substance between the bond wires and the source electrode. This solder layer (comprising tin, silver, and copper) serves as a mediator that enables electrical connection without requiring direct welding, thus reducing composite resistance and improving device reliability.
2Manufacturing precision
If multiple wires are connected between source electrode and lead tips, then wire interconnect resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the functions of multiple wire connections into a single unified solder layer application process. By applying a continuous solder layer across the source electrode surface, multiple wire attachment points are created simultaneously, reducing wire interconnect resistance without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent performs preliminary action by pre-applying the solder layer to the source electrode before wire attachment. This preliminary solder deposition creates ready-to-connect surfaces for multiple wires, simplifying the subsequent wire bonding process and reducing overall manufacturing complexity while achieving low resistance connections.
3Manufacturing precision
If welding process is used to create ball bonds, then electrical connection is established, but the destructive nature of welding limits resistance reduction
Solution Approach 1:
The patent converts the harmful effect of welding (high heat, material damage) into a beneficial non-destructive process. By replacing welding with solder attachment, the process eliminates the destructive aspects while achieving superior electrical connection with lower contact resistance, effectively turning the limitation into an advantage.
Solution Approach 2:
The patent substitutes the mechanical welding process with a metallurgical bonding process using solder. Instead of using mechanical force, heat, and pressure to create welds, the invention uses controlled solder melting and solidification to create strong, low-resistance electrical connections that are less destructive to the materials involved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces wire interconnect resistance, enhancing the performance of field-effect transistors by enabling increased current carrying capability and improving yield by eliminating the destructive welding process.
Implementation Method 1
allowing for reflow and solidification of solder to create a low-resistance conductive medium between the leads and the source electrode
Data Source
AI summary
A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires. The wires, which preferably are made of copper, then may be bonded to the electrically conductive layer by melting the solder paste, preferably by heating the leadframe, allowing the solder to reflow and wet the wires, and then cool to produce a low resistance mass between the leads.