Flexible Die Embedding with Patterned Adhesion

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Solution Overview

Problem

Traditional chip packaging technologies are two-dimensional, limiting miniaturization and requiring precise placement and high-density interconnections, which can lead to chip breakage and alignment challenges during pressure application, especially for thin chips with fine pitches.

Innovation Solution

A method involving attaching non-bumped dies to a flexible substrate with a patterned adhesion promoter, allowing for embedding and testing before embedding, using a flexible and electrically isolating polyimide layer with a fan-out metallization to reduce pressure on chips and enable relaxed pitch connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If traditional two-dimensional chip packaging is used, then routing space is available, but signal path length is minimized and miniaturization is limited

Engineering Contradiction:
Improvesignal path lengthVSAvoidminiaturization capability
Core Design Contradiction:
Length of moving objectVSProductivity

Solution Approach 1:

The patent transitions from two-dimensional planar packaging to three-dimensional embedding, where chips are vertically embedded within the substrate rather than placed on the surface. This dimensional change allows signal paths to be routed through multiple layers and via holes, significantly reducing signal path length while enabling higher density interconnections and improved miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If precise placement and high-density interconnections are used, then routing capability is improved, but chip breakage and alignment challenges increase

Engineering Contradiction:
Improverouting capabilityVSAvoidchip breakage risk
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies adhesion promoters to the substrate before embedding the chips, creating pre-formed adhesive regions that guide chip placement. This preliminary action ensures proper alignment and secure bonding without requiring excessive placement precision or applying high pressure during assembly, thereby reducing chip breakage risk while maintaining routing capability.

Inventive Principle:
Principle #10Preliminary action

3Strength

If pressure is applied during placement, then chip bonding is achieved, but thin chips with fine pitches are more likely to break

Engineering Contradiction:
Improvechip bonding strengthVSAvoidchip integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent introduces adhesion promoters as intermediary substances between the substrate and chips. These promoters create chemically active bonding surfaces that achieve strong adhesion through chemical bonding rather than mechanical pressure, allowing thin chips with fine pitches to be bonded securely without applying damaging forces during the placement process.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Manufacturing precision

If alignment precision is increased, then connection accuracy is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies adhesion promoters locally at specific embedding positions on the substrate rather than uniformly across the entire surface. This creates localized adhesive regions that guide chip placement with high precision while keeping the rest of the substrate simple, thereby achieving accurate alignment without increasing overall manufacturing process complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the creation of ultra-thin, flexible chip packages that are bendable and reduce the risk of chip breakage, allowing for more relaxed alignment constraints and efficient embedding in 3D stacks, while facilitating the testing of chips before embedding.

Implementation Method 1

a) providing a flexible substrate with a patterned adhesion promoter

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentEP1811565B1Method for embedding dies
Publication Date: 2016.05.04 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • EP1811565B1 patent drawingFigure 1(a)~1(d)
  • EP1811565B1 patent drawingFigure 2A~2F
  • EP1811565B1 patent drawingFigure 3

AI summary

Manufacturing a semiconductor device involves forming (701, 801, 802,803,804) a first flexible film (11) on a rigid carrier substrate (1), attaching (703, 704, 705, 805, 806, 807, 808) a die (3) to the flexible film, so as to leave contacts (6) on the die exposed, forming (706, 809) a wiring layer (4) to contact the contacts of the die, and releasing (706, 809) the flexible film where the die is attached, from the carrier. An area of the first flexible film where the die is attached can have a lower adhesion to the rigid carrier substrate than other areas. Then the releasing can involve cutting the first flexible film to release a part of the area of lower adhesion, and leave an area of higher adhesion. A combined thickness of the die, the first flexible film and the wiring layer can be less than 150µm, so the device is bendable. Devices can be stacked.