Flexible Sheet FinFET Structure for Channel Width Tuning
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Solution Overview
Problem
Existing multi-bridge-channel (MBC) transistors face challenges in achieving optimal performance-power-area (PPA) benefits due to limitations in flexible device design, particularly in advanced process nodes, as conventional designs lack flexibility in channel region widths to meet varying performance requirements across different circuit applications.
Innovation Solution
Implementing a flexible sheet structure in MBC transistors by adjusting the width of active regions and channel regions to create transistors with varying channel widths, allowing for optimized performance-power-area (PPA) benefits through layout modifications and mask data preparation, enabling the use of different channel region widths for specific transistor needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional MBC transistor designs with fixed channel widths are used, then manufacturing simplicity is maintained, but adaptability to different performance requirements is reduced
Solution Approach 1:
The active region is segmented into multiple sections with different width dimensions, allowing each section to form transistors with different channel widths. This segmentation enables the same device structure to provide multiple performance characteristics, resolving the contradiction between adaptability and complexity by creating variability through geometric division rather than multiple device types.
Solution Approach 2:
Different sections of the active region are given different local geometric properties (width dimensions), where each section's dimensions are optimized for specific performance requirements. This local quality approach allows high-performance sections with larger channel widths to coexist with low-power sections with smaller channel widths within a single unified device structure.
2Power
If channel region width is increased to improve power handling capability, then power handling capability is enhanced, but leakage current increases
Solution Approach 1:
The active region is divided into multiple sections with different width dimensions, allowing the device to provide both high-power handling capability (through larger width sections) and low leakage current (through smaller width sections) within the same device structure, thus resolving the trade-off between these two opposing requirements.
Solution Approach 2:
The channel width parameter is varied across different sections of the active region, with some sections having larger widths for high power handling and other sections having smaller widths for low leakage current. This parameter variation within a unified structure allows simultaneous optimization of both power handling capability and leakage control.
Data Source
AI summary
Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes patterning a top portion of a substrate, thereby forming a fin-like structure protruding from the substrate, forming a dummy gate structure across the fin-like structure, the dummy gate structure being directly above the first portion and the second portion of the fin-like structure, recessing the fin-like structure with the dummy gate structure as an etch mask, thereby forming recesses on both sides of the dummy gate structure, growing epitaxial features in the recesses, and replacing the dummy gate structure with a metal gate structure. The fin-like structure has a first portion with a first width and a second portion with a second width that is smaller than the first width. The metal gate structure engages both the first portion and the second portion of the fin-like structure.