Flexible Substrate Package Carrier with Chip Accommodating Cavity
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Solution Overview
Problem
Current semiconductor packaging technologies, such as system in package (SiP) and package on package (PoP), are limited by package area and pad pitch, restricting the effective expansion of chip disposition space.
Innovation Solution
A package carrier with a flexible substrate and build-up structures forming a chip accommodating cavity, enhanced by a patterned barrier and conductive layer, allows for increased chip disposition space through a simplified manufacturing process that utilizes the flexible substrate as a core layer for forming the cavity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging technologies (SiP, PoP) are used, then package area and pad pitch are maintained, but chip disposition space cannot be effectively expanded
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional packaging by forming a chip accommodating cavity through the substrate. The cavity is created by removing a portion of the substrate to form a through-hole, allowing chips to be disposed in the third dimension (vertical depth), thereby significantly increasing chip disposition space without expanding the package footprint area.
2Volume of moving object
If complex manufacturing processes are used to create chip cavities, then chip accommodating structures can be formed, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple manufacturing operations into a single substrate removal step. The chip accommodating cavity is formed by directly removing a portion of the substrate to create a through-hole, merging the cavity formation, wiring layer routing, and structural support creation into one integrated process, thereby reducing manufacturing complexity while achieving the desired three-dimensional chip accommodation structure.
Data Source
AI summary
A package carrier including a flexible substrate, a first build-up structure and a second build-up structure is provided. The flexible substrate has a first surface and a second surface opposite to each other, and has a first opening connected between the first surface and the second surface. The first build-up structure is disposed on the first surface and covers the first opening. The second build-up structure is disposed on the second surface and has a second opening, and the first opening and the second opening are connected to each other to form a chip accommodating cavity together. In addition, a manufacturing method of the package carrier and a chip package structure having the package carrier are also provided.