Flexible TSV Interfaces for Universal Memory Routing
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Solution Overview
Problem
Existing memory systems are inefficient and costly due to bulky designs and variable timing skews in signal routing, making them unsuitable for both CPU and GPU applications, as they require specialized signal routing and are limited by fixed sizes determined by address and data signals.
Innovation Solution
The use of through-silicon via (TSV) technology with multiplexing and steering logic circuits allows for flexible data signal routing between integrated circuit dice, enabling a universal die design that can support various data sizes and configurations, such as a 'memory cube' for CPU and GPU, by using hybrid bonding and micro-bump technologies for efficient die-to-die connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional memory systems use fixed data widths and dedicated routing for CPU or GPU applications, then the system can be optimized for specific purposes, but the system becomes bulky and cannot adapt to other applications
Solution Approach 1:
The patent implements universal TSV circuits that can function as either local memory or pass-through routing to remote memory, allowing the same hardware infrastructure to serve both CPU and GPU applications. The TSV circuits include multiplexers that can selectively connect to local memory arrays or continue signals to other dice, enabling a single memory system to adapt to different computational workloads without requiring separate dedicated systems.
Solution Approach 2:
The memory system employs dynamic configuration through steering logic circuits and multiplexers that can change the data path routing in real-time. The TSV circuits can dynamically switch between operating modes (local memory access vs. remote memory access) based on the computational requirements, allowing the system to adapt its behavior rather than being fixed for a single application type.
2Adaptability or versatility
If memory systems use dedicated signal routing for specific data widths, then timing skew is reduced, but the system requires separate routing for different applications and becomes less flexible
Solution Approach 1:
The patent merges multiple routing functions into a single TSV circuit infrastructure. The same TSV circuits carry both local and remote addresses, data signals, and control signals, eliminating the need for separate dedicated routing paths for different memory configurations. This consolidation reduces overall routing complexity while maintaining the ability to support various data widths and configurations through selective activation of circuit components.
Solution Approach 2:
The patent introduces steering logic circuits and multiplexers as intermediary elements that manage the complex routing decisions. These intermediaries receive signals from multiple sources (local memory, remote memory through TSVs) and direct them to appropriate destinations, simplifying the overall routing architecture by centralizing the decision-making logic rather than requiring complex distributed routing for each configuration.
3Adaptability or versatility
If memory systems are designed with fixed sizes based on address and data signals, then the design is simplified, but the system cannot support larger or variable data widths
Solution Approach 1:
The patent implements a nested memory architecture where local memory arrays are embedded within each die, and remote memory arrays are accessible through TSV connections to other dice. This nested structure allows the system to support variable data widths by combining multiple memory layers - smaller local arrays provide fast access for immediate needs, while larger remote arrays provide extended capacity, effectively creating a hierarchical memory system that adapts to different data width requirements.
4Productivity
If separate memory systems are designed for CPU and GPU applications, then each system is optimized for its specific purpose, but the overall system becomes bulky and costly
Solution Approach 1:
The patent creates a universal memory system that can efficiently serve both CPU and GPU applications through configurable TSV circuits. The same physical infrastructure supports different access patterns and data widths required by different processors, eliminating the need for separate dedicated memory systems while maintaining optimization for each application type through software-controlled configuration of the TSV routing and memory allocation.
Data Source
AI summary
An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.