Flip Chip Bump Array Crosstalk Reduction

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Solution Overview

Problem

The existing flip chip bump array design with a necked down region in signal traces creates high impedance and increases signal-to-signal crosstalk due to tightly coupled signal traces.

Innovation Solution

A bump array design with alternating signal and non-signal bumps, where each signal bump is surrounded by power and ground bumps, reducing signal-to-signal crosstalk and eliminating neckdowns in the package substrate, and a pin array mirroring this design to improve the electrical connection and reduce impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If signal traces are tightly coupled to achieve compact layout, then area is reduced, but signal-to-signal crosstalk increases

Engineering Contradiction:

Improvepackage substrate areaVSAvoidsignal-to-signal crosstalk

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces non-signal bumps (ground bumps and power bumps) as intermediary elements positioned between adjacent signal bumps. These intermediary bumps act as shields that block electromagnetic coupling between signal traces, thereby reducing crosstalk while maintaining compact layout. The ground bumps specifically serve as reference planes that reduce the loop area for signal return paths, further mitigating crosstalk.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a nested arrangement where non-signal bumps (ground and power) are positioned between and around signal bumps in a hierarchical pattern. This nesting creates multiple layers of shielding at different levels, with inner signal bumps surrounded by non-signal bumps that are themselves surrounded by outer signal bumps, effectively containing electromagnetic fields and reducing crosstalk in a compact footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If signal traces are tightly coupled for compact design, then area is reduced, but impedance control becomes difficult

Engineering Contradiction:

Improvepackage substrate areaVSAvoidimpedance control

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The non-signal bumps (ground and power bumps) serve as intermediary reference planes that stabilize the characteristic impedance of signal traces. By positioning these reference planes in close proximity to signal traces through the intermediary non-signal bumps, the patent ensures consistent impedance control without requiring large trace spacing, thus maintaining compact area while achieving precise impedance matching.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If necked down regions are used in signal traces for routing, then layout flexibility is improved, but high impedance regions are created

Engineering Contradiction:

Improvetrace routing flexibilityVSAvoidimpedance consistency

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the problematic necked down regions from the signal trace design. Instead of constricting trace width for routing, the invention uses alternating non-signal bumps to create open spaces that allow trace routing without creating high impedance regions. This extraction of the necking concept eliminates the impedance discontinuity while preserving layout flexibility.

Inventive Principle:

Principle #2Taking out (Extraction)

4Object-affected harmful factors

If alternating signal and non-signal bumps are used to reduce crosstalk, then signal quality is improved, but bump array complexity increases

Engineering Contradiction:

Improvesignal-to-signal crosstalkVSAvoidbump array configuration

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the bump array into distinct functional groups: signal bumps, ground bumps, and power bumps. This segmentation allows each type of bump to be optimized for its specific function while arranged in a systematic alternating pattern. The segmentation simplifies the design process by providing clear guidelines for bump placement and reduces the complexity of analyzing and troubleshooting the bump array configuration.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9332629B2Flip chip bump array with superior signal performance

Publication Date: 2016.05.03 INTEGRATED DEVICE TECH INC

AI summary

An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.