In-situ Cavity Flip Chip Packaging Using Dielectric Barriers
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Solution Overview
Problem
Conventional packaging methods for RFICs and MEMS devices require complex assembly procedures and additional process steps, such as lid attachment and maze patterning, which increase cost and reduce package efficiency, making it difficult to achieve smaller, lower-cost, high-reliability devices with under-die cavities.
Innovation Solution
A flip chip packaging process that forms under-die cavities in situ during die bonding using thermosonic bonding and dielectric barriers, such as SU8 polymer, to prevent molding compound from entering the cavity, eliminating the need for complex patterning and lid attachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods with lid attachment and maze patterning are used, then under-die cavities can be formed for MEMS devices, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The invention extracts and eliminates the complex lid attachment and maze patterning steps from the packaging process. Instead of using conventional methods requiring separate lid wafer attachment and complex photolithographic patterning, the patent uses a simplified approach where the cavity is formed directly during the molding process by strategic placement of the die and control of molding compound flow, removing unnecessary process steps while maintaining cavity integrity
Solution Approach 2:
The invention merges the cavity formation process with the die bonding and molding process. Rather than performing cavity formation as a separate step requiring lid attachment and maze patterning, the patent integrates cavity creation into the standard flip-chip packaging flow, where the cavity forms naturally during molding compound application, combining multiple functions into a single streamlined process
2Reliability
If conventional packaging methods with additional process steps are used, then under-die cavities can be formed, but manufacturing cost increases
Solution Approach 1:
The invention removes the expensive lid wafer attachment step and complex photolithographic maze patterning processes from the manufacturing flow. By eliminating these costly specialized steps and using standard molding processes instead, the patent significantly reduces manufacturing cost while maintaining the essential cavity function for MEMS device operation
Solution Approach 2:
The invention makes the standard molding process multi-functional by enabling it to perform both the protective encapsulation function and the cavity formation function simultaneously. This universal approach eliminates the need for separate specialized processes, reducing tooling costs and manufacturing complexity while achieving the same reliability outcomes
3Reliability
If conventional packaging methods are used, then cavities can be formed, but package size is increased
Solution Approach 1:
The invention extracts and removes the bulky lid structure and maze patterning elements from the package design. By eliminating these additional structural components and using a minimalist cavity approach where only the essential air gap is maintained, the patent achieves compact packaging while preserving the necessary cavity volume for MEMS mechanical motion
Solution Approach 2:
The invention uses thin molding compound layers to define the cavity boundaries instead of thick rigid lid structures. The molding compound forms a thin encapsulating layer that provides protection while maintaining a compact overall package size, replacing the need for bulky conventional lid and maze structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the assembly process, reduces costs, and enables the creation of smaller, high-reliability RFICs and MEMS devices with under-die cavities, improving package efficiency and mechanical integrity while maintaining high signal quality.
Implementation Method 1
forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die... flow of the molding compound is blocked by the barrier to provide a cavity
Implementation Method 2
bonding the die to a substrate in a flip chip configuration... Bonding the die to the substrate includes causing contact between the barrier and the substrate
Data Source
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AI summary
A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.