Flip-Chip Device Thermal Stress Reduction
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Solution Overview
Problem
Existing electronic devices with flip-chip mounted device chips on wiring substrates face issues with airtightness and heat dissipation when sealed with resin, and thermal stress occurs due to differing thermal expansion coefficients between the substrate, device chips, and sealing unit, affecting reliability.
Innovation Solution
An electronic device design featuring a wiring substrate with flip-chip mounted device chips having exposed bumps, a junction substrate with a thermal expansion coefficient equal to or less than the device chips, and a metal sealing unit that covers the junction substrate to improve airtightness and heat dissipation, while controlling thermal stress on the bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If device chips are sealed with resin, then manufacturing cost is reduced, but airtightness and heat dissipation deteriorate
Solution Approach 1:
The sealing structure is segmented into multiple functional layers: a lower sealant layer for primary sealing and an upper cap structure with through-holes for heat dissipation and airtightness. This segmentation allows each layer to perform its specific function optimally while working together to resolve the contradiction between cost-effective manufacturing and reliable sealing.
Solution Approach 2:
Different regions of the sealing structure have different properties: the lower sealant layer provides sealing functionality, while the upper cap structure with through-holes provides heat dissipation and maintains airtightness. This local differentiation of properties allows the system to simultaneously achieve cost reduction through simplified manufacturing and reliability through specialized functional zones.
2Ease of manufacture
If gaps exist between device chips and wiring substrate, then assembly is simplified, but thermal expansion coefficient mismatches cause stress on bumps
Solution Approach 1:
A lower sealant layer acts as an intermediary substance between the device chips and the wiring substrate. This intermediary layer compensates for thermal expansion coefficient mismatches by providing a compliant interface that absorbs thermal stresses, thereby preventing stress concentration on the bumps while maintaining the simplified gap structure.
Solution Approach 2:
The introduction of the lower sealant layer changes the mechanical and thermal parameters of the interface between device chips and wiring substrate. The sealant layer's material properties (viscosity, thermal expansion coefficient, elasticity) are selected to optimize stress distribution, transforming the rigid interface into a compliant one that accommodates thermal expansion differences.
3Productivity
If device chips are flip-chip mounted through bumps, then connection density is increased, but thermal expansion coefficient differences cause stress on bumps
Solution Approach 1:
The lower sealant layer serves as a mediator between the bumps and the surrounding structure. It distributes thermal stresses away from the bumps by providing a compliant interface, thereby protecting the high-density bump connections from stress-induced failures while maintaining connection density.
Solution Approach 2:
The lower sealant layer provides beforehand cushioning for the bumps against thermal expansion stresses. By being in place before thermal cycling occurs, it pre-establishes a stress-absorbing interface that protects the bumps from future thermal shock and cyclic loading.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances airtightness, heat dissipation, and reliability by reducing thermal stress on the bumps, enabling downsizing and reducing the device's height while maintaining improved junction reliability.
Implementation Method 1
a sealer that covers the junction substrate, and seals the plurality of device chips
Implementation Method 2
since respective thermal expansion coefficients of the wiring substrate, the device chips and a sealing unit are different from each other, a stress occurs in the bumps
Data Source
AI summary
An electronic device includes: a wiring substrate; a plurality of device chips that are flip-chip mounted on an upper surface of the wiring substrate through bumps, have gaps which expose the bumps between the device chips and the upper surface of the wiring substrate, and include at least one device chip that has a substrate having a thermal expansion coefficient more than a thermal expansion coefficient of the wiring substrate; a junction substrate that is joined to the plurality of device chips, and has a thermal expansion coefficient equal to or less than the thermal expansion coefficient of the substrate included in the at least one device chip; and a sealer that covers the junction substrate, and seals the plurality of device chips.