Flip Chip Mounting with Differential Solder Melting Points
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Solution Overview
Problem
The miniaturization and increasing density of semiconductor apparatuses face challenges due to slight displacement of semiconductor chips causing solder bridges between adjoining bumps in conventional flip chip mounting structures, leading to reduced manufacturing yields and limited design freedom.
Innovation Solution
A wiring board with electrode pads and solder pieces of varying spacings, where solder pieces on larger spacings have a lower melting point, allowing for self-alignment of semiconductor components without creating bridges, and enabling the use of dummy pads for improved design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If solder pieces are formed at smaller spacings to enable miniaturization, then device density increases, but solder bridges occur between adjoining bumps due to chip displacement
Solution Approach 1:
The patent applies local quality by assigning different melting points to solder pieces based on their spatial location. Solder pieces at larger spacings have lower melting points than those at smaller spacings, allowing selective melting and reflow only at specific locations to prevent bridges while maintaining high-density connections
Solution Approach 2:
The patent changes the melting point parameter of solder pieces according to their position on the wiring board. By varying the melting point based on spacing distance, the system enables precise control over which solder joints are affected during reflow, preventing bridge formation in high-density areas
2Volume of moving object
If chip spacing is reduced to achieve miniaturization, then apparatus size decreases, but positioning accuracy deteriorates due to displacement effects
Solution Approach 1:
The patent implements local quality by creating zones with different solder properties based on spacing. Areas with larger spacing use lower melting point solder that can be selectively reflowed to improve alignment, while high-density areas maintain higher melting point solder to prevent unwanted bridging
Solution Approach 2:
The patent applies preliminary action by pre-positioning solder pieces with differentiated melting points before chip mounting. This allows the reflow process to selectively affect only certain areas, enabling preliminary alignment correction before final bonding occurs
3Adaptability or versatility
If dummy pads are added to improve positioning freedom, then design flexibility increases, but device complexity increases
Solution Approach 1:
The patent applies universality by enabling electrode pads to serve multiple functions. Pads with larger spacing serve dual purposes as both electrical connection points and positioning reference points for selective reflow, eliminating the need for separate dummy pads and reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of electronic component positioning, prevents solder bridges, and contributes to the miniaturization and increased density of semiconductor apparatuses by allowing for accurate alignment and flexible design configurations.
Implementation Method 1
solder pieces on electrode pads of greater spacing have a melting point lower than that of the solder pieces on electrode pads of smaller spacing
Implementation Method 2
improve the alignment precision of the electronic component placed on the wiring board without creating a bridge or the like between the protruding electrodes
Data Source
AI summary
A flip chip mounting method for improving the accuracy of positioning of a semiconductor chip and avoiding a short circuit between protruding electrodes even when the protruding electrodes are formed at smaller spacings. The method comprises: placing a semiconductor chip on a wiring board, the semiconductor chip having protruding electrodes formed at a relatively small spacing and at a relatively large spacing, the wiring board having electrode pads corresponding to the respective protruding electrodes and solder pieces formed on the respective pads; heating the semiconductor chip and the wiring board to a temperature at which only the solder pieces on the electrode pads of greater spacing melt; performing self alignment of the semiconductor chip by the melted solder pieces; and heating the semiconductor chip and the wiring board further to a temperature at which the protruding electrodes and the solder pieces on the electrode pads of smaller spacing melt.