Semiconductor Module Terminal Layout for Low-Parasitic Inductance
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Solution Overview
Problem
Existing power supply circuits for step-down DC/DC converters suffer from surge voltage generation due to parasitic inductance in conductive paths, which can damage transistors, and extending transistor on/off transition times to reduce surge voltage leads to increased power loss.
Innovation Solution
The semiconductor module includes a semiconductor device with a specific terminal and substrate configuration that minimizes parasitic inductance by optimizing the conductive path layout and using flip-chip connections, reducing power loss while maintaining effective voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the power supply voltage is increased, then the voltage conversion efficiency is improved, but a surge voltage is generated in the conductive path due to parasitic inductance which may damage the transistors
Solution Approach 1:
The patent extracts and addresses the parasitic inductance problem by introducing a dedicated parasitic inductance measurement circuit that separates the measurement function from the normal power conversion operation. This allows the surge voltage caused by parasitic inductance to be measured and compensated without affecting the high voltage operation efficiency.
Solution Approach 2:
The patent implements feedback control by measuring the parasitic inductance voltage drop through dedicated sensing circuits and using this information to adjust the switching timing or voltage compensation. This feedback mechanism enables the system to maintain high power supply voltage while compensating for surge voltage effects in real-time.
2Object-affected harmful factors
If the on/off transition time of transistors is extended, then the surge voltage is reduced, but the power loss due to transistor operation increases
Solution Approach 1:
The patent changes the approach from modifying transistor switching parameters (transition time) to modifying the circuit topology and measurement parameters. By introducing dedicated sensing circuits and changing how parasitic inductance is measured and compensated, the system reduces surge voltage without extending transition times, thereby avoiding increased power loss.
3Device complexity
If a conventional conductive path layout is used, then the device complexity is reduced, but the parasitic inductance increases leading to surge voltage generation
Solution Approach 1:
The patent segments the conductive path into distinct functional sections: power transmission paths, sensing paths, and compensation paths. By separating these functions into different conductive path segments, the patent reduces parasitic inductance in critical measurement and control sections while maintaining overall device simplicity.
Solution Approach 2:
The patent introduces intermediary sensing circuits and measurement paths that act as mediators between the high-power conductive paths and the control circuits. These intermediary elements allow accurate parasitic inductance measurement without being directly affected by the high current and voltage in the main power paths.
Data Source
AI summary
A semiconductor module includes: a substrate; and a semiconductor device that is located on one side of the substrate in a first direction and is conductively bonded to the substrate, wherein the semiconductor device includes: a first terminal, a second terminal, and a third terminal; a semiconductor element that is located on one side of the first terminal, the second terminal, and the third terminal in the first direction; and a sealing resin that covers the semiconductor element, wherein the semiconductor element includes a first circuit and a second circuit that are connected in series with each other, wherein the first circuit is electrically connected to the first terminal and the third terminal, wherein the second circuit is electrically connected to the second terminal and the third terminal, wherein the sealing resin has a bottom surface facing the substrate.