Flip Chip Contact Pad Sidewall Wetting for Density
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Solution Overview
Problem
The larger contact pads required for manufacturing alignment tolerances in flip chip semiconductor packages limit metal signal trace routing density and reduce the number of contacts per unit area, impacting the efficiency and density of integrated circuits.
Innovation Solution
A new design rule (Psize=SRO+2*SRR−2X) allows for smaller contact pads by enabling the solder bump to overlap and wet the sidewall of the contact pad, maintaining electrical and metallurgical connectivity while increasing trace routing density and contact pad density per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact pad size is increased to ensure solder resist opening alignment, then manufacturing reliability is improved, but trace routing density and contact pad density are reduced
Solution Approach 1:
The patent transitions from a two-dimensional contact pad design to a three-dimensional structure by adding vertical sidewalls to the contact pad. This dimensional change allows the solder bump to connect to both the top surface and sidewalls of the contact pad, effectively increasing the connection area without increasing the planar footprint, thus maintaining high density while ensuring reliable solder attachment.
Solution Approach 2:
The patent applies a solder paste mask pattern that is deliberately smaller than the contact pad opening, creating a preliminary configuration where the solder bump is positioned to overlap the contact pad sidewalls. This preliminary arrangement ensures that during the reflow process, the solder will naturally wet and attach to the sidewalls, providing enhanced mechanical and electrical connection without requiring larger contact pads.
2Productivity
If contact pad size is reduced to increase trace routing density, then trace routing density and contact pad density are improved, but manufacturing alignment tolerance is compromised
Solution Approach 1:
By adding vertical sidewalls to create a three-dimensional contact pad structure, the patent enables smaller planar contact pads while maintaining reliable solder connections. The sidewalls provide additional attachment surface area that compensates for the reduced top surface area, allowing high trace routing density without sacrificing manufacturing alignment tolerance.
Solution Approach 2:
The patent changes the geometric parameters of the contact pad by introducing sidewall height and modifying the aspect ratio. This parameter transformation allows the contact pad to maintain adequate connection area through vertical extension rather than horizontal expansion, thereby enabling reduced pad size for higher density while preserving connection reliability.
3Reliability
If contact pad size is increased to ensure full metal area exposure, then solder connection reliability is improved, but the number of contacts per unit area is reduced
Solution Approach 1:
The three-dimensional contact pad structure with vertical sidewalls provides additional connection surface area in the vertical dimension. This allows the solder bump to attach to both the top surface and sidewalls, effectively increasing the total connection area without increasing the planar footprint, thereby enabling more contacts per unit area while maintaining solder connection reliability.
Solution Approach 2:
The patent merges the top surface and sidewalls of the contact pad into a unified three-dimensional connection structure. This combination allows the solder bump to simultaneously attach to multiple surfaces, effectively consolidating the connection area into a compact vertical structure that increases contact density while ensuring reliable solder attachment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced contact pad size increases trace routing density and contact pad density without compromising manufacturing reliability or electrical functionality, enhancing the performance and efficiency of semiconductor devices.
Implementation Method 1
The solder bumps are formed by a reflow process applied to solder material deposited on metal contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate.
Implementation Method 2
a reflow process applied to solder material
Data Source
AI summary
A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.