Flip Chip Packaging via Patterned Insulating Layers
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Solution Overview
Problem
Conventional flip-chip packaging methods face challenges such as high production costs, limited yield, and reliability issues due to incompatible thermal expansion coefficients between substrates and underfill layers, requiring multiple reflow processes and one-piece substrate handling.
Innovation Solution
A flip-chip packaging method involving a substrate with patterned insulating layers and conductive materials, where chips are directly mounted onto pre-cured adhesive layers on the substrate, eliminating the need for underfill layers and reducing the number of packaging steps, using materials like photosensitive or non-photosensitive resins and conductive pastes for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip packaging methods are used with underfill layers and multiple reflow processes, then electrical connections between chips and substrates are achieved, but thermal expansion incompatibility causes substrate cracks and reduces product reliability
Solution Approach 1:
The patent removes the underfill layer from the packaging structure, eliminating the source of thermal expansion incompatibility that causes substrate cracks. The connection structure relies solely on solder balls/bumps for both electrical connection and mechanical support, extracting the problematic intermediate layer.
Solution Approach 2:
The patent applies different material properties at different locations: the substrate and chip are designed with specific thermal expansion coefficients that are compatible with each other, while the solder balls provide both electrical conductivity and mechanical flexibility to accommodate thermal stress locally at the connection points.
2Reliability
If multiple reflow processes are performed for packaging, then solder balls are properly attached and electrical connections are established, but production costs increase and manufacturing complexity increases
Solution Approach 1:
The solder balls are pre-mounted on the chip or substrate in a separate preparation step before the final packaging assembly. This preliminary action allows the solder balls to be precisely positioned and pre-heated, so that only a single reflow process is needed during final assembly to complete the electrical and mechanical connection.
3Reliability
If substrates are packaged one piece at a time, then each package can be individually quality-controlled, but production yield is limited and overall cost increases
Solution Approach 1:
The substrate is designed as a multi-array structure with multiple independent packaging regions, each containing its own chip and solder ball connections. This segmentation allows the entire substrate array to be processed simultaneously in a single reflow cycle, enabling parallel production while maintaining individual quality control for each package unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method decreases material usage, enhances packaging quality, reduces thermal expansion issues, and increases production yield by simplifying the process and eliminating the need for multiple reflow steps, thereby lowering overall costs and improving product reliability.
Implementation Method 1
forming an insulating layer with patterns on the substrate and the connecting pads and a plurality of openings by partially exposing the upper surface of the connecting pads
Implementation Method 2
a plurality of conductive bumps is formed over the bottom surface of the chip; mounting the chips over the surface of the IC package substrate unit
Data Source
AI summary
A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed on the substrate and the connecting pads and a plurality of openings by partially exposing the upper surface of the connecting pads. Next, a conductive material is disposed within each opening. Next, a plurality of chips is provided, in which a plurality of conductive bumps is formed over the bottom surface of the chip. Lastly, the chips are mounted over the surface of the IC package substrate unit and the substrate is separated into a plurality of flip chip package structures, in which the surface of each flip chip package structure includes at least one chip.