Flip-Chip Stacked Die Packaging With Through Vias
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in achieving high integration and reducing package volume while maintaining efficient signal transmission, particularly with the development of smaller line widths and multi-chip systems.
Innovation Solution
The process involves bonding dies using flip chip technology, covering them with a molding material, and filling through vias with a conductive material for electrical connection, allowing for smaller chip sizes and reduced signal transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If multiple chips are arranged into a single package to achieve high integration, then the packaging volume and fabrication cost are reduced, but the signal transmission path and manufacturing complexity increase
Solution Approach 1:
The package structure is segmented into distinct functional layers: molding material for encapsulation, through vias for vertical interconnection, and conductive materials for electrical routing. This segmentation allows each component to be optimized independently while maintaining overall integration, reducing manufacturing complexity despite multi-chip integration
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional stacking with through vias extending vertically through the molding material. This dimensional change enables shorter signal paths between stacked chips while maintaining compact packaging volume, and the layered structure simplifies the manufacturing process by separating interconnection functions into distinct vertical layers
2Length of moving object
If flip chip technology is used to bond dies, then the chip size and signal transmission path are reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The molding material serves as an intermediary that encapsulates the flipped chips and provides a matrix for forming through vias. This intermediary structure protects the precise flip-chip bonds while enabling subsequent via formation and conductive material deposition, effectively decoupling the bonding precision requirement from subsequent manufacturing steps
Solution Approach 2:
The flip-chip bonding is performed first before forming the molding material and through vias. This preliminary action establishes the precise chip positioning and short signal paths early in the process, allowing subsequent steps to work with the already-positioned chips without requiring the same level of precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more integrated chips with improved signal transmission efficiency and reduced fabrication costs, suitable for high-frequency devices.
Implementation Method 1
A molding material is formed to entirely cover the second dies and the wafer
Implementation Method 2
A conductive material is formed to fill the through via onto the molding material for electrical connecting to external connections
Implementation Method 3
A plurality of second dies are bonded on the first dies by using flip chip technology
Data Source
AI summary
A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.