Flip Chip Underfill Dam for Parasitic Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices using flip chip mounting, the arrangement of chip-type capacitative elements away from the semiconductor element leads to increased parasitic inductance and capacitance, degrading electric properties and preventing miniaturization due to the need for a larger wiring board area, while underfill resins with good fluidity and wettability can result in insufficient mechanical support and resin flow issues.
Innovation Solution
A semiconductor device design featuring a first and second conductive pattern surrounding the semiconductor element to act as a dam for the underfill resin, preventing its extension and ensuring the chip-type capacitative elements are placed close to the semiconductor element, thereby reducing parasitic effects and optimizing substrate area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chip-type capacitative elements are arranged away from the semiconductor element, then wiring board area increases, but parasitic inductance and capacitance increase degrading electric properties
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive patterns that extend upward from the wiring board surface to surround the semiconductor element. This three-dimensional arrangement allows capacitative elements to be positioned close to the semiconductor element without increasing the horizontal wiring board area, thereby reducing parasitic inductance and capacitance while maintaining compact form factor.
Solution Approach 2:
The conductive patterns are segmented into multiple sections that collectively surround the semiconductor element. These segmented conductive structures create multiple shielding paths, effectively reducing parasitic effects while allowing compact arrangement of capacitative elements near the semiconductor element.
2Reliability
If underfill resin with good fluidity and wettability is used, then void formation is prevented, but mechanical support becomes insufficient and resin flow issues occur
Solution Approach 1:
The conductive patterns are formed as dams before the underfill resin is applied. These pre-formed conductive barriers prevent the resin from flowing outward excessively, counteracting the high fluidity of the underfill resin. This allows the use of resins with good wettability and low viscosity for void prevention while the conductive dams provide the necessary mechanical containment and support.
Solution Approach 2:
The conductive patterns serve as an intermediary structure between the underfill resin and the semiconductor element. They act as a mechanical barrier that controls resin flow while allowing the resin to maintain its beneficial flow and wettability characteristics for filling gaps and preventing voids.
3Reliability
If conductive patterns are formed close to semiconductor element, then parasitic effects are reduced, but underfill resin may extend and cover capacitative elements
Solution Approach 1:
The conductive patterns are strategically positioned and dimensioned to serve dual functions: they are close enough to the semiconductor element to reduce parasitic effects, while simultaneously acting as dams to prevent underfill resin from extending outward and covering the capacitative elements. The height and positioning of these conductive patterns are optimized to create an effective barrier against resin flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design stabilizes the electric properties of the semiconductor device by minimizing parasitic inductance and capacitance, allowing for a more compact form factor and improved mechanical support of the semiconductor element.
Implementation Method 1
The underfill resin is ordinarily supplied using a capillary action
Data Source
AI summary
A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.