Flip-Flop Buffer Bypass for Timing Error Calibration
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Solution Overview
Problem
High integration density in semiconductor integrated circuits leads to production variations, causing timing errors due to delayed circuit operations, which are difficult to address without increasing circuit complexity and reducing yield.
Innovation Solution
A semiconductor integrated circuit design that includes a flipflop with a buffer circuit controlled by an enable signal, allowing data calibration to meet operation speed requirements, thereby improving chip yield by bypassing the master latch to transmit input data when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock frequency is reduced to avoid timing errors, then timing error is avoided, but the operation speed cannot satisfy the required speed
Solution Approach 1:
The buffer circuit dynamically switches between high impedance state and signal transmission state based on the enable signal. When timing error is detected, the enable signal activates the buffer to transmit the correct data from the master latch, allowing the circuit to maintain high clock frequency while correcting timing errors dynamically rather than reducing the clock frequency statically
2Reliability
If another latch circuit and comparison circuit are added to detect and calibrate timing errors, then timing error detection capability is improved, but the circuit scale becomes large
Solution Approach 1:
The invention merges the error detection and correction functions into the existing flip-flop structure by adding a buffer circuit that shares the same data path. The buffer circuit is controlled by an enable signal that activates only when timing error is detected, combining multiple functions (data transmission, error correction, and conditional bypass) into a single integrated structure rather than adding separate latch and comparison circuits
Solution Approach 2:
The buffer circuit acts as an intermediary between the master latch and the output, selectively transmitting data based on the enable signal. This intermediary structure allows the circuit to maintain its original data path while adding error correction capability, avoiding the need for parallel comparison circuits and reducing overall circuit complexity
Data Source
AI summary
A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted.