Asynchronous Reset Flip-Flop Layout With Gated Clock Clearing
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Solution Overview
Problem
Scan flip-flops, particularly those with asynchronous reset, occupy significant silicon area and consume more power due to their large size and high transistor count, leading to routing congestion and increased power consumption, which becomes exacerbated as technology scales down.
Innovation Solution
Implementing a gated clock signal to clear the master/slave latch of a resettable scan flip-flop when an asynchronous clear signal is asserted, relocating the 'clear' logic from the slave latch to the clock logic, thereby reducing the size of the layout and power consumption by minimizing the number of transistors switching during reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clear logic is included in the slave latch of a resettable scan flip-flop, then the flip-flop can be reset asynchronously, but the layout area increases and routing congestion occurs
Solution Approach 1:
The clear logic is extracted from the slave latch and relocated to the clock logic portion of the layout. This extraction removes the congested clear logic from the slave latch area, reducing layout area and routing congestion while preserving the asynchronous reset functionality through the master latch
2Reliability
If clear logic is included in the slave latch, then asynchronous reset is enabled, but routing congestion increases
Solution Approach 1:
The clear logic is extracted from the slave latch and placed in the clock logic portion, which reduces routing congestion in the previously congested slave latch area. The extraction simplifies the routing topology by relocating the clear logic to a less congested region
3Reliability
If transistors in the slave latch are coupled to clock signal for reset, then reset functionality is achieved, but power consumption increases
Solution Approach 1:
The clear logic transistors are extracted from the slave latch and relocated to the clock logic portion. This relocation ensures that during reset assertion, the transistors are controlled by the gated clock signal rather than toggling continuously, thereby reducing dynamic power consumption while maintaining reset functionality
4Productivity
If technology scaling is applied to reduce chip size, then integration density increases, but layout of resettable scan flip-flops becomes increasingly difficult
Solution Approach 1:
By extracting the clear logic from the slave latch and relocating it to the clock logic portion, the invention reduces the transistor count and layout complexity in the slave latch area. This extraction makes the layout process increasingly feasible as technology scales to smaller nodes with more aggressive design rules
Data Source
AI summary
A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.