Flip-Flop Circuit with Parallel Slave Latches for Area Reduction
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Solution Overview
Problem
Existing data processing circuits require multiple logic circuits with the same configuration, leading to increased circuit area, which is undesirable and inefficient.
Innovation Solution
A flip flop circuit with a master latch circuit, multiple slave latch circuits, and an output selection circuit that allows for the selection of data from multiple slave latch circuits, reducing the need for multiple logic circuits and minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logic circuits with the same configuration are provided to execute parallel signal processing, then the parallel processing capability is improved, but the circuit area increases
Solution Approach 1:
The patent applies multi-functionality by designing a single logic circuit that can process multiple types of signals through different operational modes. The flip-flop circuit is configured to handle both synchronous data transfer (using clock signal CLK) and asynchronous data transfer (using gate signal GAT), allowing one logic circuit to perform functions that would traditionally require separate dedicated circuits for each protocol type.
Solution Approach 2:
The patent implements dynamics by making the logic circuit's operation mode changeable based on control signals. The circuit can dynamically switch between synchronous and asynchronous operation modes through the control signal selection circuit, which selects between clock signal CLK and gate signal GAT based on the mode signal MODE. This dynamic reconfigurability allows a single circuit to adapt to different processing requirements without requiring multiple fixed-configuration circuits.
2Productivity
If multiple flip flop circuits are provided for parallel data holding, then the data processing capacity is improved, but the device complexity increases
Solution Approach 1:
The patent applies merging by combining multiple slave latch circuits (first slave latch circuit 140_1 and second slave latch circuit 140_2) into a single integrated structure with a shared master latch circuit. Instead of providing completely separate flip-flop circuits for different data paths, the patent merges them into one circuit unit that can service multiple data streams through the slave latch circuits, reducing overall device complexity while maintaining parallel processing capacity.
Solution Approach 2:
The patent applies segmentation by dividing the data processing function into distinct stages within the flip-flop circuit: master latch circuit for receiving and initial processing, slave latch circuits for parallel data holding, and output selection circuit for routing. This segmentation allows the circuit to handle multiple data streams through different pathways while using a unified control mechanism, thereby increasing processing capacity without proportionally increasing overall complexity.
3Area of stationary object
If a single logic circuit is used to perform multiple signal processing tasks, then the circuit area is reduced, but the adaptability requirement increases
Solution Approach 1:
The patent applies multi-functionality by designing the logic circuit with universal input interfaces that accept different signal types (synchronous clock signals and asynchronous gate signals) and different data formats. The control signal selection circuit enables the logic circuit to adapt its operation based on the mode signal, allowing it to process I2C communication data, synchronous serial data, and other protocols through the same hardware structure.
Solution Approach 2:
The patent implements dynamics through the mode signal MODE that enables the logic circuit to change its operational characteristics in real-time. The control signal selection circuit dynamically switches between using clock signal CLK and gate signal GAT based on the mode signal, allowing the single logic circuit to adapt to different communication protocols and data transfer requirements without requiring separate dedicated circuits for each type.
Data Source
AI summary
Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.