Non-Volatile Flip-Flop Power Gating With Unified Enable Control
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Solution Overview
Problem
The complexity of analyzing and controlling enable signals for non-volatile flip-flops in semiconductor logic circuit devices increases when different enable signals are used for clock and data acquisition circuits, leading to complex configuration and generation of enable signals.
Innovation Solution
A semiconductor circuit device with a first clock gating circuit, a non-volatile flip-flop, an acquisition circuit, and a power gating circuit that coordinates power source control using separate enable signals for clock and data acquisition, allowing for simplified power management and reduced complexity in signal analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate enable signals are used for clock control and data acquisition in non-volatile flip-flop circuits, then functional flexibility is improved, but analysis complexity and circuit configuration complexity increase
Solution Approach 1:
The patent combines the clock control enable signal and data acquisition enable signal into a single unified enable signal that controls both functions simultaneously. This merging approach maintains the functional flexibility of having separate control capabilities while eliminating the complexity of analyzing and coordinating multiple enable signals, as the single signal provides synchronized control to both the clock gating circuit and the acquisition circuit.
2Adaptability or versatility
If separate enable signals are used for clock control and data acquisition, then independent control capability is improved, but circuit configuration complexity increases
Solution Approach 1:
The unified enable signal serves multiple functions simultaneously: it controls the clock gating circuit to gate the clock signal, and it controls the acquisition circuit to acquire data from the non-volatile flip-flop. This multi-functional approach provides independent control capability over both clock and data acquisition while simplifying the overall circuit configuration by eliminating the need for separate enable signal generation and coordination logic.
Data Source
AI summary
A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.