Flip-Flop Multiplexer Reset Layout for Simpler Signal Routing
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Solution Overview
Problem
Highly integrated semiconductor integrated circuits face increased signal routing complexity due to the implementation of flip-flops, which complicates the design and operation of data storage devices used in sequential logic circuits.
Innovation Solution
Incorporating a multiplexer with a reset input in the flip-flop design, along with a master and slave latch configuration, to efficiently manage and reset signals based on clock and scan enable signals, thereby simplifying the signal routing and operation of flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of flip-flops is increased to improve data storage capacity and integration, then the data storage capability is enhanced, but the signal routing complexity increases
Solution Approach 1:
The multiplexer is configured to selectively output different signals (data input signal or scan input signal) based on control signals, allowing the same hardware structure to serve multiple functions including normal data storage and scan test operations, thereby reducing the need for separate dedicated routing paths
Solution Approach 2:
The patent combines the data input path and scan input path into a single multiplexer structure, merging previously separate signal routing paths into one unified component that handles both types of inputs, thus reducing overall routing complexity
2Reliability
If traditional flip-flop structures are used without integrated reset functionality, then the basic data storage function is maintained, but the device requires additional external reset circuitry increasing complexity
Solution Approach 1:
The reset functionality is merged into the existing multiplexer structure by adding a reset input signal that can force the multiplexer output to a predetermined state, eliminating the need for separate external reset circuitry while maintaining reliable reset operation
Solution Approach 2:
The multiplexer is designed to perform multiple functions including normal data input, scan test input, and reset operations, allowing a single component to handle what would traditionally require multiple separate circuits, thereby reducing overall device complexity
Data Source
AI summary
An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.