Flipped Conductor Patch Lamination for Ultra-Fine PCB Tracks
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Solution Overview
Problem
Existing methods for integrating ultra-fine conductive tracks on printed circuit board (PCB) substrates face challenges such as reduced adhesion of copper tracks, difficulty in forming small vias, non-linear stretching of laminated layers, and registration issues due to thermal expansion and material mismatch.
Innovation Solution
A method involving a non-conductive substrate with a conductive electroplating seed layer, photoresist application, and electroplating conductive material in defined channels, followed by adhering a non-conductive layer and removing excess material, to create ultra-fine conductive tracks that are laminated into a prepreg layer for secure embedding and precise placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching is used to create fine conductive tracks on PCB substrates, then conductive tracks can be formed, but adhesion of copper tracks to substrate becomes greatly reduced as track width decreases
Solution Approach 1:
The conductive track structure is segmented into multiple functional layers: a substrate layer, an electroplating seed layer, and a final conductive material layer. This segmentation allows each layer to perform its specific function optimally - the substrate provides mechanical support, the seed layer provides adhesion and electroplating capability, and the final layer provides low-resistance conduction, thereby resolving the adhesion problem while maintaining fine track dimensions
Solution Approach 2:
The electroplating seed layer is applied in advance to the substrate before the final conductive material is deposited. This preliminary action ensures that the substrate surface is pre-prepared with a layer that has both adhesive properties and electroplating capability, allowing subsequent conductive materials to bond strongly even when track widths are reduced to fine dimensions
2Ease of manufacture
If conventional PCB lamination processes are used, then layers can be assembled, but non-linear stretching occurs making layer registration difficult
Solution Approach 1:
The lamination process parameters are optimized and controlled, including temperature, pressure, and curing time profiles. By carefully controlling these parameters, the thermal expansion and mechanical deformation of layers during lamination are minimized, reducing non-linear stretching and improving layer registration precision while still enabling effective layer assembly
3Manufacturing precision
If additive processes are used for substrate design and fabrication, then ultra-fine tracking layers can be created, but these processes are limited to outer layers and are proprietary
Solution Approach 1:
The electroplating-based additive process is designed to be universally applicable to multiple substrate types and conductive material configurations. The process can create conductive features not only on outer layers but also on inner layers and on various substrate materials, making it a versatile solution that is not limited to specific locations or substrate types, thereby increasing adaptability while maintaining ultra-fine precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures secure adhesion of fine conductive tracks, allows for accurate placement and registration, minimizes thermal mismatch, and facilitates the formation of small vias, addressing the limitations of traditional PCB fabrication methods.
Implementation Method 1
electroplating a conductive material in the defined wiring channels
Data Source
AI summary
A method includes providing a layer of non-conductive material having a conductive electroplating seed layer formed on a surface thereof; applying a photoresist layer over the surface of the conductive electroplating seed layer; and defining wiring channels in the photoresist resist layer. The method includes electroplating a conductive material in the defined wiring channels; adhering a non-conductive layer over the photoresist layer and the plated conductive material in the wiring channels; and removing the layer of non-conductive material and the conductive electroplating seed layer.