Flipped-Gate Voltage Reference With Leakage Compensation
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Solution Overview
Problem
Conventional voltage reference circuits using bipolar junction transistors (BJTs) and CMOS devices are susceptible to substrate noise, leading to inaccurate temperature-independent reference voltages, especially at elevated temperatures.
Innovation Solution
A voltage reference circuit employing a flipped gate transistor with an anti-doped gate electrode and a sizing arrangement between transistors to produce a temperature-independent reference voltage, utilizing current mirrors and a voltage boxing region to compensate for leakage currents and maintain accuracy across varying temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bipolar junction transistors (BJTs) are used to form bandgap references, then a reference voltage signal can be provided, but the circuit becomes sensitive to substrate noise from majority or minority carriers
Solution Approach 1:
The patent introduces an isolated well structure (n-well for NPN transistors, p-well for PNP transistors) as an intermediary layer between the transistor and the substrate. This well acts as a mediator that electrically isolates the transistor from substrate noise while maintaining the transistor's functionality, thereby resolving the contradiction between achieving accurate reference voltage and avoiding substrate noise sensitivity
Solution Approach 2:
The patent segments the substrate structure by creating a separate isolated well region within the substrate. This segmentation divides the original substrate-transistor interface into two distinct regions: the well region housing the transistor and the surrounding substrate region. This structural segmentation enables electrical isolation and reduces noise coupling, addressing the accuracy versus noise sensitivity contradiction
2Device complexity
If CMOS devices are used without reverse-junction isolation, then device complexity is reduced, but substrate noise susceptibility increases
Solution Approach 1:
The patent employs reverse-biased junctions (such as n-well to p-substrate or p-well to n-substrate junctions) as intermediary isolation structures. These junctions act as mediators that block noise propagation from the substrate to the CMOS devices while maintaining relatively simple device architecture, thus resolving the contradiction between device complexity and noise susceptibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively isolates the voltage reference from substrate noise, ensuring temperature independence and accuracy of the reference voltage, even at high temperatures, thereby enhancing the reliability of voltage regulation systems.
Implementation Method 1
A voltage reference circuit employing a flipped gate transistor with an anti-doped gate electrode and a sizing arrangement between transistors to produce a temperature-independent reference voltage
Implementation Method 2
utilizing current mirrors and a voltage boxing region to compensate for leakage currents and maintain accuracy across varying temperatures
Implementation Method 3
A voltage reference circuit employing a flipped gate transistor with an anti-doped gate electrode and a sizing arrangement between transistors to produce a temperature-independent reference voltage
Data Source
AI summary
A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.