Frequency-Locked Loop Clocking With Chopper Noise Cancellation
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Solution Overview
Problem
Frequency locked loop circuits in electronic products often introduce noise into clock signals, leading to instability and jitter, which existing solutions fail to adequately address.
Innovation Solution
A frequency locked loop circuit comprising an operational circuit, impedance circuits, and a switching circuit that periodically switches the terminals to reduce noise by modulating low-frequency noise to high-frequency regions, where it can be filtered out, using a chopper operational amplifier and low-frequency pass filter to achieve noise cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency locked loop circuit is applied to prevent clock signal noise, then clock signal stability is improved, but the circuit introduces additional noise and jitter
Solution Approach 1:
The patent applies periodic switching action through a switching circuit that periodically connects and disconnects the operational amplifier from the feedback network. This periodic action modulates low-frequency noise to high-frequency regions where it can be filtered out, thereby reducing the noise and jitter introduced by the frequency locked loop circuit while maintaining clock signal stability
Solution Approach 2:
The patent converts the harmful low-frequency noise generated by current sources and the frequency generation circuit into a beneficial effect by modulating it to high-frequency regions through periodic switching. The high-frequency noise is then easily filtered out by the low-pass filter, transforming the original harmful noise into a benefit for noise reduction and jitter cancellation
2Measurement precision
If noise filtering is applied to reduce jitter, then clock signal accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the noise filtering function with the existing frequency locked loop circuit by integrating a switching circuit and low-pass filter into the feedback path. This combination approach achieves jitter reduction and clock signal accuracy improvement without requiring a completely separate filtering system, thereby limiting the increase in circuit complexity
Solution Approach 2:
The switching circuit acts as an intermediary element that periodically modulates the operational signal, and the low-pass filter serves as an intermediary that selectively removes high-frequency noise components. These intermediary elements enable effective noise filtering and jitter reduction while maintaining a relatively simple circuit architecture
Data Source
AI summary
A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.