Floating Body Cell Structures for DRAM Charge Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional dynamic random access memory (DRAM) cells face challenges in reducing cell area while maintaining charge retention and reliability due to the scaling of silicon-on-insulator (SOI) transistors, which leads to increased noise susceptibility and decreased operating margin as the floating body size decreases.
Innovation Solution
The implementation of multi-gate floating body cell structures with a back gate and another gate associated with the floating body, where the back gate functions as a capacitor, increasing charge storage and retention time, and integrating these structures with CMOS devices to enhance memory density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the SOI substrate is reduced to prevent charge loss in smaller floating bodies, then charge loss from SRH recombination is reduced, but the amount of charge accumulated in the floating body decreases and noise susceptibility increases
Solution Approach 1:
The patent implements a nested gate structure where a first gate is positioned within the floating body and a second gate is positioned on the surface, creating a nested configuration. This allows the floating body to be controlled by multiple gates at different levels, enabling independent optimization of charge storage and noise immunity without requiring substrate thinning.
Solution Approach 2:
The patent transitions from conventional planar gate control to a three-dimensional nested gate architecture. The first gate embedded within the floating body and the second gate on the surface create vertical control dimensions, allowing charge accumulation to be maintained while noise susceptibility is reduced through spatial separation of control functions.
2Productivity
If the cell size is reduced to increase memory density, then more cells can be integrated, but the volume of the floating body decreases leading to less charge storage and increased charge loss
Solution Approach 1:
By nesting the first gate within the floating body structure, the patent enables effective control of charge accumulation in smaller floating bodies. The embedded gate position allows for optimized electric field distribution that maintains charge storage capacity even as floating body volume decreases due to scaling.
Solution Approach 2:
The patent changes the structural parameters of gate configuration from conventional surface-only gates to a nested arrangement with gates at different depths. This parameter change enables maintaining adequate charge storage in scaled-down floating bodies by optimizing the electric field distribution throughout the reduced volume.
3Quantity of substance
If conventional DRAM capacitor structures are used to maintain charge storage, then capacitance requirements are met, but cell area increases and integration density decreases
Solution Approach 1:
The patent makes the floating body serve multiple functions: it acts as both the active transistor region and the charge storage element. The nested gate structure enables the floating body to accumulate and retain charge without requiring a separate capacitor structure, thereby eliminating the need for additional capacitor area in the cell layout.
Solution Approach 2:
The patent merges the transistor channel region and the charge storage region into a single floating body structure. By combining these previously separate functions into one integrated element controlled by nested gates, the design eliminates the need for distinct capacitor structures and reduces overall cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases memory density and reliability by minimizing signal fluctuation and charge loss, providing longer retention times and improved operational margins through enhanced charge storage and isolation from source and drain regions.
Implementation Method 1
the back gate functions as a capacitor, increasing charge storage and retention time
Implementation Method 2
enhanced charge storage and isolation from source and drain regions
Data Source
AI summary
Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.