Floating-Body DRAM Voltage Control for Read/Write Reliability
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face issues with erroneous reading or rewriting due to strong capacitive coupling between the word line and the floating body, making it difficult to commercially introduce such memory devices.
Innovation Solution
A semiconductor-element-including memory device is designed with a structure that includes a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the voltages applied to these layers are controlled to retain or discharge positive holes generated by impact ionization, optimizing the data retention and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but strong capacitive coupling between word line and floating body causes erroneous reading or rewriting
Solution Approach 1:
The patent introduces a control mechanism that mediates the capacitive coupling effect between the word line and floating body. By controlling the word line voltage timing and magnitude relative to the bit line voltage, the system manages the noise interference to prevent erroneous reading or rewriting while maintaining the high-density capacitor-less structure.
Solution Approach 2:
The patent adjusts operational parameters including word line voltage levels, bit line voltage timing, and drain voltage conditions to optimize the balance between maintaining strong capacitive coupling for high density and minimizing noise-induced errors. Specific voltage thresholds and timing sequences are established to control the coupling effect.
2Speed
If strong capacitive coupling between word line and floating body is maintained, then memory operation speed is improved, but noise interference from word line voltage changes increases
Solution Approach 1:
The patent applies preliminary actions by pre-charging bit lines and controlling word line activation timing before actual read or write operations. This preliminary voltage control prepares the floating body in a state that is less susceptible to noise from subsequent word line voltage changes, thereby maintaining fast operation while reducing errors.
Solution Approach 2:
The patent employs periodic refresh operations and structured voltage cycling sequences that periodically reset and stabilize the floating body voltage. This periodic control mitigates the accumulation of noise effects while maintaining the rapid response characteristics needed for high-speed memory operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise interference from word line voltage changes, enhancing the reliability of data reading and writing, and facilitating the commercial introduction of capacitor-less single-transistor DRAMs.
Implementation Method 1
positive holes generated by impact ionization
Data Source
AI summary
A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.