Floating Body Memory Cell Vertical Segmentation
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Solution Overview
Problem
Conventional floating body memory cells suffer from charge leakage and poor data retention due to the small size of the floating body, which leads to signal fluctuation and weakened signals, especially at higher temperatures.
Innovation Solution
The design enhances the floating body memory cell by increasing its size and using a bias gate and dielectric material to store charges remotely from the source and drain regions, with a passage coupling the first and second portions of the floating body, allowing for enhanced charge retention and reduced recombination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating body size is increased to store more charge and improve data retention, then the charge storage capacity and signal stability are improved, but the device area increases and scalability is reduced
Solution Approach 1:
The patent divides the floating body into multiple portions arranged vertically at different heights above the substrate, rather than expanding horizontally. This vertical stacking allows increased charge storage capacity in the vertical dimension while maintaining a compact horizontal footprint, resolving the contradiction between data retention and device area.
Solution Approach 2:
Multiple floating body portions are nested vertically within a compact horizontal space, with each portion positioned at a different height. This nesting arrangement maximizes charge storage capacity within a limited device area by utilizing the vertical dimension, thereby improving data retention without proportionally increasing the device footprint.
2Device complexity
If the floating body is positioned close to source and drain regions for compact design, then device integration is improved, but charge leakage and recombination increase
Solution Approach 1:
The floating body is segmented into multiple isolated portions positioned at different vertical heights. This segmentation creates electrical isolation between charge storage regions and high-field regions near source and drain, reducing charge leakage and recombination while maintaining compact horizontal integration.
Solution Approach 2:
By positioning floating body portions at different vertical heights, the patent creates vertical separation between charge storage regions and source/drain regions. This vertical distancing reduces electric field coupling and charge leakage while maintaining horizontal compactness, resolving the contradiction between device integration and charge retention.
3Reliability
If a bias gate is added to control floating body voltage and improve data retention, then charge control and signal stability are improved, but device complexity increases
Solution Approach 1:
The bias gate is positioned to control only specific portions of the floating body structure, applying voltage control where most needed for charge retention. This partial control approach improves charge stability without requiring complete control of the entire floating body, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved data retention and minimized signal fluctuation by allowing more charge to be stored, resulting in a more stable signal compared to conventional structures.
Implementation Method 1
using a bias gate and dielectric material to store charges remotely from the source and drain regions
Implementation Method 2
using a bias gate and dielectric material to store charges
Data Source
AI summary
Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.