Floating Body Transistor Memory Cell Design
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving efficient data storage and retrieval due to limitations in scaling and stability of memory cells, particularly in volatile memory types like DRAM.
Innovation Solution
The development of a semiconductor memory cell with an electrically floating body transistor, which features a floating body region capable of having two stable states, allowing for higher cell current in one state compared to the other. This design includes a gate surrounding the floating body on all sides, a buried well layer, and a substrate, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional 1T/1C memory cell is used, then data storage is achieved through capacitor charge, but the cell size is larger and scaling to smaller feature sizes is more difficult
Solution Approach 1:
The patent removes the capacitor component from the conventional 1T/1C memory cell architecture, extracting the charge storage function and replacing it with a floating body transistor that utilizes impact ionization to generate and store carriers, thereby reducing cell size while maintaining functionality
Solution Approach 2:
The patent changes the fundamental storage mechanism from capacitor charge to floating body carrier accumulation through impact ionization, altering the physical parameters of the memory cell to achieve smaller dimensions while preserving data storage capability
2Stability of the object's composition
If the floating body region is charged to indicate memory state, then bi-stability is achieved, but charge leakage and recombination can cause data loss
Solution Approach 1:
The patent implements a feedback mechanism where impact ionization continuously generates carriers in the floating body to compensate for charge leakage and recombination, maintaining the stored state without requiring external refresh operations
Solution Approach 2:
The floating body transistor performs self-refresh through impact ionization, where the stored carriers themselves generate additional carriers to replace those lost to leakage and recombination, eliminating the need for external refresh circuits
3Reliability
If impact ionization is used to generate holes for compensation, then charge leakage is compensated, but additional energy is required for carrier generation
Solution Approach 1:
The impact ionization process is self-driven by the stored carriers in the floating body, which generate additional carriers through collision with the lattice, eliminating the need for external energy input beyond the initial charge storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory cell design achieves bi-stability, allowing for higher cell current in one stable state, which enhances data storage and retrieval efficiency, addressing the limitations of existing memory technologies.
Implementation Method 1
a floating body region configured to be charged to a level indicative of a state of the memory cell
Implementation Method 2
This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination
Data Source
AI summary
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.