Floating Contact Hole Etching to Prevent Gate Voids
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Solution Overview
Problem
The increase in thickness of the oxide layer of the salicide block in semiconductor devices leads to voids between polysilicon gates, affecting device performance and yield, especially in Bipolar-CMOS-DMOS processes with smaller line widths, which complicates the integration of logic devices and memories and increases chip area and cost.
Innovation Solution
A method for forming a floating contact involves depositing a salicide block with a controlled oxide layer thickness between 400 Å to 600 Å, using a photoresist pattern with a retention region to slow down etching and prevent void formation, allowing for sufficient withstand voltage without thickening the oxide layer, thereby enabling integration of devices with smaller line widths and reducing chip area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the thickness of the oxide layer of the salicide block is increased to ensure sufficient withstand voltage, then the withstand voltage is improved, but voids appear between polysilicon gates affecting device performance and yield
Solution Approach 1:
The patent introduces a photoresist retention region in the floating contact pattern before etching. This retention region remains during the etching process to provide preliminary protection, preventing void formation between polysilicon gates. After etching, the retention region is removed. This preliminary protective action allows the oxide layer thickness to be reduced while maintaining reliability.
Solution Approach 2:
The photoresist retention region acts as an intermediary element during the etching process. It temporarily protects the regions between polysilicon gates from excessive etching that would cause voids. The retention region mediates between the need for sufficient withstand voltage (thinner oxide) and the need to prevent voids, enabling both goals to be achieved.
2Strength
If the thickness of the oxide layer of the salicide block is increased to ensure sufficient withstand voltage, then the withstand voltage is improved, but the chip area increases due to inability to integrate devices with smaller line widths
Solution Approach 1:
The photoresist retention region is introduced before etching to control the etching process. This allows devices with smaller line widths to be integrated without causing voids, thereby reducing chip area while maintaining sufficient withstand voltage through the oxide layer.
Solution Approach 2:
The patent changes the etching process parameters by using a photoresist retention region that is selectively removed. This enables precise control of the etching depth and protection of critical regions, allowing smaller device dimensions to be fabricated without compromising withstand voltage requirements.
3Strength
If the thickness of the oxide layer of the salicide block is increased to ensure sufficient withstand voltage, then the withstand voltage is improved, but manufacturing complexity increases due to void formation issues
Solution Approach 1:
The photoresist retention region is formed as part of the standard photolithography process before etching. This preliminary step integrates smoothly into existing manufacturing flows, avoiding the need for complex additional process steps while preventing void formation and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures sufficient withstand voltage without voids, allowing for the integration of logic devices and memories with smaller line widths, reducing chip area, lowering costs, and improving economic benefits by maintaining device performance and yield.
Implementation Method 1
a photoresist retention region having a light transmittance opposite to that of a remaining region of the floating contact pattern
Data Source
AI summary
A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.