Floating Gate Cavities for NAND Memory Capacitive Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scaling NAND memory cells leads to increased capacitive coupling between floating gates, causing inaccurate sensing of threshold voltages and charge levels due to their proximity, which existing methods struggle to address effectively.
Innovation Solution
Incorporating dielectric regions around the floating gates to reduce capacitive coupling, either by creating cavities within the gates filled with dielectric materials or by recessing the dielectric into the gate surfaces, which helps in minimizing the capacitive area and maintaining the control gate-to-floating gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND memory cells are scaled to increase storage density, then storage capacity is improved, but capacitive coupling between floating gates increases causing inaccurate threshold voltage sensing
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent floating gates. This dielectric layer acts as a mediator that reduces the direct capacitive coupling between floating gates while allowing the memory cells to maintain their scaled-down dimensions for high storage density.
Solution Approach 2:
The harmful capacitive coupling effect is extracted or removed from the system by introducing the dielectric material between floating gates. This extraction of the harmful electromagnetic interaction allows the memory cells to be scaled closer together without sacrificing threshold voltage sensing accuracy.
2Productivity
If floating gates are positioned closer together to increase cell density, then storage density is improved, but capacitive coupling interference increases
Solution Approach 1:
The dielectric material serves as a protective intermediary that blocks the harmful capacitive coupling interference between closely spaced floating gates. This allows the floating gates to be positioned closer together for increased storage density while the dielectric prevents the generation of harmful electromagnetic interference.
Solution Approach 2:
The dielectric material converts the potentially harmful close proximity of floating gates into a beneficial arrangement. By introducing the dielectric, the close spacing that would normally create harmful capacitive coupling is transformed into an acceptable configuration that achieves high storage density while maintaining electrical isolation.
3Measurement precision
If dielectric regions are added around floating gates to reduce capacitive coupling, then threshold voltage sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The dielectric material is applied locally only in the regions between floating gates where capacitive coupling occurs, rather than uniformly throughout the entire device. This localized application reduces the overall complexity increase while effectively addressing the threshold voltage sensing accuracy problem in the critical areas.
Solution Approach 2:
The dielectric regions are positioned in the spatial dimension between floating gates, creating a three-dimensional structure that addresses the capacitive coupling problem. By utilizing the vertical and lateral spacing between components, the solution adds structural complexity only where necessary without fundamentally redesigning the entire transistor architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces capacitive coupling between floating gates, maintaining the coupling ratio and reducing the need for higher programming voltages, thereby improving the accuracy of charge level sensing and storage in NAND memory cells.
Implementation Method 1
capacitive coupling between floating gates may produce inaccurate sensing of threshold voltages and, thus, charge levels
Implementation Method 2
Incorporating dielectric regions around the floating gates to reduce capacitive coupling
Data Source
AI summary
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.