Floating-Gate Memory Cell Structure for Logic and Memory Integration
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Solution Overview
Problem
Existing manufacturing processes for nonvolatile memory cells often require separate areas for logic devices and memory devices on a semiconductor substrate, limiting the integration density and efficiency.
Innovation Solution
A manufacturing method for a nonvolatile memory cell that integrates core devices, IO devices, and memory cells on the same semiconductor substrate, using a specific structure comprising a semiconductor substrate, well regions, dielectric layers, floating gate layers, gate layers, and conducting lines to form a functional memory cell array alongside a peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If separate areas are used for logic devices and memory devices on a semiconductor substrate, then device functionality is ensured, but integration density is limited
Solution Approach 1:
The patent merges the logic device area and memory device area into a single integrated structure where core devices and memory cells share the same semiconductor substrate and manufacturing process flow. The gate layers, dielectric layers, and doped regions are formed simultaneously for both device types, eliminating the need for separate fabrication areas and improving integration density while reducing layout complexity.
Solution Approach 2:
The patent employs universal gate layers (first and second gate layers) and common dielectric layers that serve dual purposes for both core devices and memory cells. The same manufacturing steps produce structures that function as either logic or memory elements, allowing the system to achieve multi-functionality on a single substrate without requiring device-specific process variations.
2Reliability
If separate manufacturing processes are used for core devices and memory cells, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent combines the manufacturing processes for core devices and memory cells into a single unified flow. The first gate layer, second gate layer, dielectric layers, and doped regions are formed using the same sequential steps for both device types, eliminating the need for separate process modules and reducing manufacturing complexity while maintaining device performance through precise structural control.
Solution Approach 2:
The patent achieves device performance optimization through parameter variations within the unified manufacturing process. By controlling the thickness, material composition, and doping concentrations of the gate layers and dielectric structures, the same process can produce both core devices and memory cells with their respective performance requirements without requiring fundamentally different manufacturing approaches.
3Reliability
If multiple gate layers and dielectric layers are formed, then memory cell functionality is achieved, but manufacturing steps increase
Solution Approach 1:
The patent merges the formation of multiple gate layers and dielectric layers into a single integrated manufacturing sequence. The first gate layer, second gate layer, and associated dielectric layers are deposited and patterned in one continuous process flow that simultaneously creates the necessary structures for both core devices and memory cells, reducing the total number of discrete manufacturing steps and improving productivity.
Solution Approach 2:
The patent performs preliminary formation of the gate layers and dielectric structures before final device differentiation. By establishing the multi-layer architecture early in the manufacturing process, subsequent steps can focus on selective doping and contact formation, rather than building the entire structure from scratch for each device type, thereby improving overall manufacturing efficiency.
Data Source
AI summary
A nonvolatile memory cell includes an N-well region, an IO gate dielectric layer, a floating gate dielectric layer, a floating gate layer, a first gate layer, a second gate layer and two p-doped regions. The floating gate dielectric layer is contacted with the surface of the N-well region. The floating gate layer covers the floating gate dielectric layer. The IO gate dielectric layer covers the surface of the N-well region and the floating gate layer. The first gate layer is contacted with IO gate dielectric layer located on the sidewall and the top surface of the floating gate layer. The second gate layer is contacted with the IO gate dielectric layer located on the sidewall of the floating gate layer. The first gate layer, the second gate layer and the floating gate layer are located over the surface of the N-well region between the two p-doped regions.