Floating-Gate Electrode Charge Retention via Silicide-Block Oxide
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Solution Overview
Problem
Conventional analog integrated circuits face challenges in achieving precise and stable reference levels due to manufacturing variations and leakage issues in capacitor dielectric films, particularly when using floating-gate technology, which requires costly additional processes and results in inconsistent diode performance at p-n junctions within polysilicon floating-gate electrodes.
Innovation Solution
A programmable analog floating-gate element is developed with both p-type and n-type regions, implemented in a CMOS environment, where the polysilicon gate electrode is protected by a silicide-block silicon dioxide film, and tunnel capacitors are used for precise charge programming and erasure, eliminating parasitic diodes and ensuring long-term charge retention without additional process complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional capacitor dielectric films (e.g., silicon nitride deposited by PECVD) are used in floating-gate trimming circuits, then the reference circuits can be trimmed at manufacture, but the trapped charge leaks over time resulting in poor long-term stability
Solution Approach 1:
The patent changes the dielectric material parameter from conventional silicon nitride to oxide semiconductor material, which fundamentally alters the electrical properties to achieve both precise initial trimming and long-term charge retention without leakage
Solution Approach 2:
The patent uses a composite structure combining oxide semiconductor dielectric layer with floating-gate electrode, creating a new material system that exhibits both high precision programming capability and excellent charge retention characteristics
2Measurement precision
If additional costly processes (deposition of dielectric films, deposition and patterning of additional conductor layers) are implemented to achieve precise and stable reference circuits, then the reference precision can be improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The oxide semiconductor dielectric layer serves multiple functions simultaneously: it acts as the capacitor dielectric for charge storage, provides the insulation layer for Fowler-Nordheim tunneling, and enables both n-type and p-type floating-gate implementations, eliminating the need for separate specialized processes
Solution Approach 2:
The patent uses the same oxide semiconductor dielectric layer for both n-channel and p-channel floating-gate devices, allowing identical manufacturing processes to be used for both transistor types without requiring additional specialized deposition or patterning steps
3Ease of operation
If conventional capacitor dielectric films are used with floating-gate technology, then trimming can be performed by electrical means, but the diode performance at p-n junctions within polysilicon floating-gate electrodes becomes inconsistent
Solution Approach 1:
The patent changes the conductivity type parameter of the floating-gate electrode from conventional polysilicon to oxide semiconductor material, which eliminates the formation of parasitic p-n junctions and their associated inconsistent diode effects while maintaining electrical programming capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides repeatable programmability, high capacitance per unit area, and compatibility with high voltage applications, enabling precise adjustment of analog levels with improved stability and reduced power consumption, suitable for high-precision ADCs and DACs.
Implementation Method 1
the polysilicon gate electrode is protected by a silicide-block silicon dioxide film
Implementation Method 2
Programming of the device is accomplished through such mechanisms as Fowler-Nordheim tunneling
Implementation Method 3
the state of the transistor is defined by charge trapped at a floating gate electrode
Implementation Method 4
Programming of the device is accomplished through such mechanisms as Fowler-Nordheim tunneling, and hot carrier injection
Data Source
AI summary
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.