Floating-Gate Cell Erase Sequencing for Program-State Precision
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Solution Overview
Problem
Existing split gate memory cell technologies face challenges in achieving precise and efficient programming and erasing operations, particularly in analog and multilevel cell (MLC) operations, leading to inaccuracies and inefficiencies in achieving desired program states.
Innovation Solution
Implementing a method of sequential erasing by applying successive first and second erase pulses with varying parameters to gradually adjust the electron charge on the floating gate, using control circuitry to monitor and adjust voltages and pulse durations, ensuring accurate targeting of the desired read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional erase pulses are applied to memory cells, then erasing operation is performed, but precision and efficiency of achieving desired program state is insufficient
Solution Approach 1:
The erase operation is divided into multiple sequential erase pulses with varying parameters. Each pulse removes a portion of the charge from the floating gate, allowing precise control over the final program state. This segmentation enables both high precision in achieving the target state and maintained efficiency through automated sequential execution.
Solution Approach 2:
The erase pulses systematically vary key parameters including voltage magnitude, pulse duration, and timing intervals. By changing these parameters across successive pulses, the method optimizes the erasing process to achieve precise program states while maintaining operational efficiency through automated parameter adjustment.
2Measurement precision
If single erase pulse is applied, then erasing operation is simple, but accuracy in achieving target read current is insufficient
Solution Approach 1:
The method incorporates feedback mechanisms where the read current is measured after each erase pulse to determine whether the target program state has been achieved. Based on this feedback, the control circuitry adjusts subsequent pulse parameters or terminates the sequence, ensuring accurate targeting of the desired read current while managing complexity through intelligent control.
Solution Approach 2:
The erase operation uses periodic sequential pulses with systematically varying parameters. This periodic action allows the system to progressively approach the target read current with controlled steps, achieving high measurement precision through multiple measurements and adjustments rather than a single complex operation.
3Adaptability or versatility
If sequential programming is used, then programming state can be adjusted, but over-programming may occur
Solution Approach 1:
Feedback control is implemented by measuring the read current after each erase pulse to verify whether the target program state has been reached. This feedback mechanism allows the system to adaptively adjust or terminate the erase sequence, providing versatility in achieving different program states while minimizing the risk of over-programming through real-time verification.
Solution Approach 2:
The method applies partial erase actions through multiple smaller pulses rather than a single large pulse. This approach provides fine-grained control over the program state adjustment, enabling versatile tuning while reducing the risk of over-programming by distributing the total erase amount across many controlled steps with intermediate verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and efficiency of programming and erasing processes, reducing the likelihood of over-programming or over-erasing, thereby improving the accuracy and reliability of memory cell states.
Implementation Method 1
applying successive first erase pulses to the memory cell to remove electrons from the floating gate
Data Source
AI summary
A method and device for erasing a memory cell with a floating gate, by applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current, and then applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved. The first erase pulses include a first parameter following a first progression that changes in value after respective ones of the first erase pulses. The first progression begins with a first value and ends with a second value. The second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses. The second progression begins with a third value that is between, and unequal to, the first and second values.