Floating Gate FIN-FET Isolation for Leakage Reduction
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Solution Overview
Problem
Current DRAM technologies face challenges in reducing junction leakage current due to high electric fields at the source and drain contact areas with the substrate, leading to increased channel length and complexity in controlling access current.
Innovation Solution
A manufacturing method for a fin field effect transistor (FIN-FET) with a floating body is developed, involving the removal of grounded gates and formation of isolation spaces filled with gate oxide to block current leakage paths, utilizing a shallow trench isolation structure and isotropic silicon etching to enhance isolation and reduce substrate interaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the feature size of recessed access device is reduced to increase channel length, then channel control is improved, but junction leakage current increases due to high electric field at source and drain contact areas
Solution Approach 1:
The invention extracts and removes the grounded gates from the device structure, replacing them with floating gates that extend into the isolation regions. This extraction eliminates the direct substrate contact path that causes junction leakage, while maintaining channel control through the floating gate structure.
Solution Approach 2:
The invention introduces floating gates as an intermediary element between the substrate and the channel region. These floating gates act as a mediator that provides electrical isolation, blocking the harmful leakage current path while still enabling channel control through capacitive coupling.
2Ease of operation
If grounded gates are used to maintain constant potential, then channel control is achieved, but current leakage path from cell sides to substrate is created
Solution Approach 1:
The invention removes the grounded gates that create leakage paths and replaces them with floating gates. The floating gates are not directly connected to ground, thereby extracting the harmful leakage path from the device structure while preserving channel control functionality.
Solution Approach 2:
The invention extends the gates into the isolation regions, adding a spatial dimension to the gate structure. This dimensional extension allows the gates to provide both channel control and electrical isolation simultaneously by occupying the isolation region space.
3Object-generated harmful factors
If isolation spaces are formed to block leakage current, then junction leakage is reduced, but device structure complexity increases
Solution Approach 1:
The invention merges the gate structure with the isolation regions by extending the floating gates into the isolation spaces. This merging combines the functions of gate control and electrical isolation into a single integrated structure, reducing overall device complexity while maintaining leakage blocking capability.
Solution Approach 2:
The floating gates serve multiple functions simultaneously: they provide channel control through their position over the channel, and they provide electrical isolation by extending into the isolation regions to block leakage paths. This multi-functionality reduces the need for separate isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces current leakage and improves data retention by increasing on-current access while maintaining constant potential across the channel, thereby enhancing the performance of DRAM devices.
Implementation Method 1
filling up gate oxide in the openings and the isolation spaces
Implementation Method 2
performing an isotropic silicon etching to form isolation spaces at the bottom which extends to the underside of the drain of the FIN FET transistor
Data Source
AI summary
A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.