Floating Gate Nonvolatile Memory Structure With Extended Portions
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Solution Overview
Problem
The data retention capability of nonvolatile memory structures deteriorates due to thin gate oxides, leading to defects and reduced reliability in multi-time programmable memory, which necessitates an improvement in the memory's ability to retain information over time.
Innovation Solution
A nonvolatile memory structure with two charge storage regions per bit is developed, utilizing a p-type substrate with PMOS transistors and floating gates, where the floating gates have extended portions overlapping with the n-type erase region, and a salicide blocking layer is applied to enhance data retention and erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate oxide under the charge storage region is made thinner to increase storage capacity, then the memory can store more information, but the data retention capability deteriorates due to defects in the thin gate oxide
Solution Approach 1:
The patent divides the charge storage function into two separate regions: a first charge storage region (first floating gate) and a second charge storage region (second floating gate). Each region can independently store charge, allowing the memory to maintain data retention reliability while increasing overall storage capacity. This segmentation eliminates the need to thin a single gate oxide layer, as each floating gate is formed over its own thicker oxide layer.
2Device complexity
If a single charge storage region is used in MTP memory, then the memory structure is simpler, but data retention capability deteriorates when gate oxide defects occur
Solution Approach 1:
The patent implements two separate charge storage regions (first and second floating gates) instead of a single storage region. Each floating gate is associated with its own select transistor and can be independently controlled. This segmentation provides redundancy against gate oxide defects while maintaining a relatively simple overall memory structure that can be integrated into existing CMOS processes.
Solution Approach 2:
The patent applies different functional qualities to different parts of the memory cell. The first floating gate stores information during program operations, while the second floating gate stores information during erase operations. Each region has optimized characteristics for its specific function, with local control through dedicated select transistors, improving overall reliability without significantly increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces bit failure rates and enhances data retention characteristics by improving erase efficiency and stability, thereby maintaining reliable information storage over time.
Implementation Method 1
each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates
Implementation Method 2
memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E
AI summary
A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.