Floating Gate Memory Device With Self-Aligned Fourth Poly Layer
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Solution Overview
Problem
Conventional methods for fabricating floating gate memory devices face challenges in maintaining a high gate coupling ratio (GCR) due to smaller buried diffusion sizes, which requires additional complex photolithographic steps and increases the risk of misprocessing and misalignment.
Innovation Solution
A self-aligned process for forming the fourth poly layer is used, increasing the inter-poly dielectric surface area between the control gate and floating gate without additional lithographic steps, thereby enhancing the GCR and reducing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional fabrication techniques are used with reduced buried diffusion sizes, then device size is reduced, but gate coupling ratio decreases
Solution Approach 1:
The patent introduces a fourth polysilicon layer stacked vertically above the existing three layers, transforming a two-dimensional lateral expansion problem into a three-dimensional vertical structure. This additional layer increases the inter-poly dielectric surface area and improves gate coupling ratio without increasing the device footprint, effectively resolving the contradiction between small device size and adequate coupling ratio
Solution Approach 2:
The fourth polysilicon layer is nested within the existing gate structure, positioned between the third polysilicon layer and the control gate. This nested configuration allows the additional coupling surface area to be integrated within the existing device boundaries, maintaining compact device size while enhancing the gate coupling ratio through the extra dielectric interface
2Reliability
If additional photolithographic steps are added to increase inter-poly area, then gate coupling ratio is improved, but process complexity increases
Solution Approach 1:
The fourth polysilicon layer is formed using a self-aligned process where the layer is deposited and patterned based on the existing third polysilicon layer structure, eliminating the need for separate photolithographic alignment steps. The preliminary formation of the first three layers automatically defines the position and area of the fourth layer, simplifying the overall fabrication process while maintaining improved gate coupling ratio
Solution Approach 2:
The self-aligned formation process allows the existing gate structure to automatically define and position the fourth polysilicon layer without requiring additional lithographic patterning steps. The process uses the existing structures to serve as their own alignment references, reducing process complexity and the risk of misalignment while achieving the desired increased inter-poly dielectric surface area
Data Source
AI summary
A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.