Floating Gate Memory Coupling Coefficient via Self-Aligning MOS
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Solution Overview
Problem
Conventional floating gate memory devices face inefficiencies in programming due to limited capacitance per unit area, which restricts the coupling coefficient and thus the speed of programming and erasing operations, leading to potential data integrity issues from repeated reads.
Innovation Solution
The solution involves synthesizing a floating gate memory device from two MOS transistors, where one acts as a capacitor and the other as a tunnel diode, with a self-aligning gate structure and ion-implanted tips to increase the capacitance ratio, enhancing the coupling coefficient and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional floating gate memory devices are used, then the device structure is simple, but the programming speed is slow due to limited coupling coefficient
Solution Approach 1:
The memory device is segmented into two separate MOS transistors (first and second transistors) with distinct functions: one serves as the floating gate transistor for data storage, while the other acts as a capacitor to enhance the coupling coefficient. This segmentation allows optimization of each component's function independently, achieving faster programming speeds without excessive overall complexity.
Solution Approach 2:
The second MOS transistor serves multiple functions: it acts as a capacitor to boost the coupling coefficient for faster programming, while also being part of the overall memory cell structure. This multi-functionality helps achieve improved programming speed without proportionally increasing device complexity.
2Productivity
If the capacitance of the MOS capacitor is increased to improve coupling coefficient, then the programming efficiency improves, but the area of silicon required increases
Solution Approach 1:
The invention changes the parameters of the second transistor to function as a capacitor with optimized capacitance value. By carefully selecting the capacitance parameters of the second transistor, the coupling coefficient is enhanced for efficient programming while controlling the silicon area required. The patent specifies that the capacitance ratio between the first and second transistors should be optimized to achieve the desired coupling coefficient without excessive area.
Solution Approach 2:
The invention merges the capacitor function directly into the second MOS transistor structure, eliminating the need for a separate discrete capacitor component. This integration reduces the overall silicon area required compared to using a separate capacitor, while still achieving the necessary capacitance ratio for improved programming efficiency.
3Ease of operation
If repeated reads are performed on floating gate memory, then data can be accessed, but read disturbances cause charge leakage and reduce data integrity
Solution Approach 1:
The enhanced coupling coefficient achieved through the capacitor-transistor configuration provides stronger feedback during programming operations, ensuring more complete charge transfer to the floating gate. This results in more stable threshold voltage shifts and greater margins against read disturbance effects, improving data integrity while maintaining ease of access.
Solution Approach 2:
The increased coupling coefficient and improved programming efficiency create larger initial charge states on the floating gate, providing a cushion against subsequent read disturbances. This prior cushioning ensures that even after multiple reads, sufficient charge remains on the floating gate to maintain data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the coupling coefficient, allowing for faster programming and erasing operations while maintaining data integrity by reducing the impact of read disturbances on stored charge.
Implementation Method 1
ion-implanted tips extending each diffusion region under adjacent gate fingers
Implementation Method 2
one MOS transistor is configured as a capacitor (MOS capacitor) and the other transistor is configured as a tunnel diode (MOS tunnel diode). The programming efficiency of this configuration depends on a coupling coefficient between the MOS capacitor and the MOS tunnel diode.
Implementation Method 3
Programming voltages can be applied to the transistor between the control gate and the substrate or source and drain diffusions to add or remove charge from the floating gate by hot carrier injection (HCI) or by Fowler-Nordheim tunneling
Data Source
AI summary
Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.