Floating-Gate MOS PUF Circuit for Secure Key Generation
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Solution Overview
Problem
Current digital circuit-based PUF implementations, such as SRAM-based and OTP structures, face challenges with bit error rates and complexity, making them difficult to integrate with large-scale digital circuits and vulnerable to deciphering security keys.
Innovation Solution
A PUF device utilizing two MOS transistors with floating gates and shared input voltage, leveraging capacitance coupling effects to generate unique random values without physical damage, allowing for a simple structure and high-security key generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF implementation is used, then PUF functionality is achieved, but device complexity increases and manufacturing precision requirements increase
Solution Approach 1:
The PUF device is divided into multiple independent PUF units, each consisting of only two MOS transistors. This segmentation approach reduces the complexity of individual units while maintaining overall PUF functionality through the collective behavior of multiple units.
Solution Approach 2:
The invention extracts and eliminates unnecessary circuit components from traditional PUF designs. By removing complex SRAM cell structures and retaining only the essential two-transistor configuration, the design achieves PUF functionality with minimal device complexity.
2Reliability
If OTP structure-based PUF implementation is used, then PUF functionality is achieved, but ease of operation deteriorates due to easy deciphering of security keys
Solution Approach 1:
The invention converts the potential vulnerability of simple structures into a security advantage. The two-transistor design without physical damage mechanisms makes it impossible to extract CRPs through physical attacks, turning structural simplicity into a security feature rather than a weakness.
Solution Approach 2:
The design preemptively prevents security key deciphering by eliminating the physical damage pathways that attackers use to extract CRPs from OTP structures. The floating gate configuration and operational mechanism are designed from the outset to resist such attacks.
3Reliability
If non-electronic PUF or analog circuit PUF is used, then PUF functionality is achieved, but device complexity increases and ease of manufacture deteriorates
Solution Approach 1:
The invention replaces non-electronic or analog PUF mechanisms with a fully electronic digital circuit implementation using standard MOS transistors. This substitution enables seamless integration with digital circuits while maintaining PUF functionality through electrical operations only.
Solution Approach 2:
The design changes the operational parameters from analog or optical domains to digital electrical domain. By operating entirely in the digital electrical domain with standard voltage levels and logic states, the PUF becomes easily manufacturable using existing digital CMOS processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a simple, high-capacity PUF implementation that is difficult to crack, enabling secure key generation and integration with standard MOS processes, suitable for applications like RFID and IoT identity authorization.
Implementation Method 1
the two MOS transistors present different turnon characteristics depending on the capacitance coupling effect, thereby implementing functions of the PUF
Data Source
AI summary
A PUF device and a method of outputting a random sequence are disclosed. The PUF device includes: at least one processing unit and at least one PUF unit, and a first PUF unit of the at least one PUF unit includes a first MOS transistor and a second MOS transistor, two sources of the two MOS transistors are connected to a same input voltage; two gates of the two MOS transistors are floating; and two drains of the two MOS transistors are respectively connected with a first processing unit, and the first processing unit is configured to: output a first random value corresponding to the first PUF unit according to a difference between two results output by the two drains of the two MOS transistors, when the input voltage is greater than or equal to a preset voltage.