Floating Gate Spacers in Substrate Trenches for Flash Memory
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Solution Overview
Problem
Current non-volatile flash memory systems face challenges in efficiently utilizing substrate area for increased storage density, particularly in NOR and NAND arrays, where floating gates often require complex voltage management and programming mechanisms that compromise efficiency.
Innovation Solution
The use of substrate trenches to position floating gates along sidewalls, with spacers formed from conductive doped polysilicon, allows for efficient use of substrate area and enables ballistic injection programming, reducing the need for complex voltage management and enhancing programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If floating gates are positioned on substrate surface in conventional NOR or NAND arrays, then voltage management and programming mechanisms become complex, but substrate area utilization is inefficient
Solution Approach 1:
The patent positions floating gates vertically along the sidewalls of substrate trenches rather than horizontally on the substrate surface. This dimensional transition from 2D surface placement to 3D vertical placement along trench walls enables efficient substrate area utilization while simplifying voltage management through the trench structure's inherent field confinement
2Device complexity
If conventional programming mechanisms are used, then voltage management is complex, but programming efficiency is reduced
Solution Approach 1:
The patent extracts the programming mechanism from complex multi-step voltage management sequences and replaces it with direct ballistic injection. By positioning floating gates in trenches and applying simplified voltage patterns to word lines and bit lines, electrons are directly accelerated onto floating gates, eliminating the need for complex programming sequences
3Quantity of substance
If substrate area is reduced for higher density, then storage density increases, but conventional floating gate positioning becomes impractical
Solution Approach 1:
The patent resolves the manufacturing impracticality by transitioning from horizontal surface placement to vertical sidewall placement along trenches. This dimensional change allows floating gates to be positioned using standard semiconductor fabrication techniques (trench formation followed by spacer deposition) while achieving high storage density through efficient substrate area utilization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the substrate surface area required for each memory cell, increases storage density, and improves programming efficiency by allowing direct electron acceleration onto floating gates, thereby enhancing the overall performance of flash memory arrays.
Implementation Method 1
enables ballistic injection programming, reducing the need for complex voltage management and enhancing programming efficiency
Data Source
AI summary
In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.