Floating Gate Transistor Memory Cell with Segmented Structure
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Solution Overview
Problem
Conventional erasable programmable non-volatile memory technologies face inefficiencies in program, erase, and read operations due to limitations in transistor design and voltage application modes, which affect storage state determination and overall memory performance.
Innovation Solution
The proposed solution involves a novel structure with four transistors (two p-type and two n-type) in separate well regions, where the floating gates of the p-type and n-type transistors are connected, and specific voltage application modes are used during program, erase, and read cycles to enhance efficiency, including the use of ramp voltages and coupling layers to improve electron injection and ejection processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor design with single floating gate is used, then device complexity is reduced, but program efficiency and erase efficiency are insufficient
Solution Approach 1:
The memory cell is divided into two separate transistor structures (first and second transistors), each with its own floating gate (first floating gate and second floating gate). This segmentation allows independent control of programming and erasing operations, improving overall efficiency while maintaining manageable device complexity through modular design
Solution Approach 2:
The first floating gate and second floating gate are connected to form a unified floating gate structure that serves both transistors. This merging enables shared charge storage functionality while allowing selective voltage application to each transistor gate, resolving the contradiction by achieving high efficiency through combined structure with independent control capabilities
2Productivity
If conventional voltage application mode is used, then operation simplicity is maintained, but read efficiency and storage state determination are insufficient
Solution Approach 1:
The patent implements dynamic voltage application modes where different voltage levels (first voltage, second voltage, third voltage) are selectively applied to different transistor gates during read operations. This dynamic voltage control enables efficient storage state determination through comparative threshold voltage analysis, improving read efficiency while managing operational complexity through systematic voltage sequencing
Solution Approach 2:
The read operation uses feedback-based threshold voltage comparison where the voltage applied to one transistor gate is adjusted based on the state of the other transistor. This feedback mechanism enables accurate storage state determination by comparing threshold voltages, improving read efficiency while maintaining ease of operation through automated state detection
3Reliability
If separate well regions are used for different transistors, then transistor isolation and control are improved, but device area increases
Solution Approach 1:
The patent utilizes vertical well regions (first well region and second well region) extending into the substrate to provide transistor isolation and control. By transitioning to vertical dimension for well formation rather than horizontal separation, the design achieves reliable transistor control while minimizing lateral area expansion, effectively resolving the contradiction between reliability and area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances program efficiency, erase efficiency, and read efficiency by optimizing electron transfer and storage state determination, allowing for improved performance in both negative and positive operation modes.
Implementation Method 1
The second p-type transistor is a floating gate transistor. The polysilicon gate 36 (also referred as a floating gate) is disposed over the second p-type transistor.
Implementation Method 2
conventional erasable programmable non-volatile memory technologies face inefficiencies in program, erase, and read operations due to limitations in transistor design and voltage application modes
Implementation Method 3
The proposed solution involves a novel structure with four transistors (two p-type and two n-type) in separate well regions, where the floating gates of the p-type and n-type transistors are connected, and specific voltage application modes are used during program, erase, and read cycles to enhance efficiency, including the use of ramp voltages and coupling layers to improve electron injection and ejection processes.
Data Source
AI summary
An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.