Self-Aligned Floating Gates With Oxidation-Blocking Spacers
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Solution Overview
Problem
The issue of tunneling oxide non-uniformity and floating-gate over-oxidation in self-aligned floating-gate/Shallow Trench Isolation (STI) process during the fabrication of non-volatile memory devices leads to misalignment and irregular shapes, hindering the scaling down of cell device sizes in advanced nanometer fabrication.
Innovation Solution
The introduction of oxidation blocking dielectric spacers along the side walls of floating-gates to encapsulate poly-silicon from oxidation during trench oxide liner formation, preserving tunneling oxide thickness and floating-gate dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature oxidation process is applied for trench liner formation, then oxide liners are formed along shallow trench walls, but floating-gate over-oxidation occurs causing tunneling oxide non-uniformity and irregular floating-gate shapes
Solution Approach 1:
A nitrogen-containing dielectric layer is introduced as an intermediary barrier between the floating-gate and the oxidation environment. This layer prevents oxygen from reaching the floating-gate during high-temperature oxidation processes, thereby eliminating over-oxidation while allowing trench oxide liners to form normally. The dielectric layer serves as a protective mediator that enables the oxidation process to proceed without harmful side effects.
Solution Approach 2:
The nitrogen-containing dielectric layer is deposited on the floating-gate surface before the high-temperature oxidation process begins. This preliminary protective action prevents oxygen diffusion to the floating-gate during subsequent oxidation steps, counteracting the potential harmful effect of over-oxidation before it can occur. The pre-applied barrier ensures that when oxidation takes place, the floating-gate remains protected.
2Manufacturing precision
If self-aligned floating-gate/STI process is used, then alignment between floating-gates and device active areas is improved, but floating-gate over-oxidation still occurs during trench liner formation
Solution Approach 1:
The nitrogen-containing dielectric layer acts as an intermediary protective barrier that allows the self-aligned floating-gate/STI process to proceed without compromising device reliability. While the process provides good alignment, the dielectric layer prevents over-oxidation that would otherwise cause functional failures, thus maintaining both alignment precision and device reliability simultaneously.
3Productivity
If device scaling down is pursued for higher density, then manufacturing cost decreases, but alignment and over-oxidation issues become more critical
Solution Approach 1:
The nitrogen-containing dielectric layer provides a protective intermediary function that becomes increasingly important as devices are scaled down. At smaller feature sizes, the margin for error in alignment and oxidation control decreases, making the dielectric barrier essential for maintaining manufacturing precision while enabling continued scaling for higher density and lower cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances tunneling oxide uniformity and maintains floating-gate integrity, enabling the scaling of non-volatile memory devices to minimum feature sizes in advanced nanometer fabrication processes.
Implementation Method 1
oxidation blocking dielectric spacers along the side walls of floating-gates to prevent over-oxidation during trench oxide liner formation
Implementation Method 2
high temperature (ranging from 750° C. ̃1100° C.) oxidation process applied for the formation of oxide liners 161 along the shallow trench walls
Data Source
AI summary
A method for forming floating gates in a non-volatile memory array is disclosed, comprising: patterning and etching portions of a hard-mask dielectric layer, a conductive layer and a tunneling oxide layer to define stacked structures over a substrate; conformally depositing a spacer dielectric layer over the substrate; etching a portion of the spacer dielectric layer to form spacers along sidewalls of each stacked structure; etching a portion of the substrate to form trenches so that the trenches and the stacked structures are alternately arranged in each row; and, growing liners on silicon walls of the trenches. Here, the hard-mask dielectric layer and the spacer dielectric layer comprise an oxidation-blocking material. Accordingly, the poly-silicon floating-gates are encapsulated in the hard-mask dielectric layer and the spacers such that the shapes of floating-gates and the tunneling oxide thickness are well preserved.