Floating Point Operand Comparison Logic
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Solution Overview
Problem
Existing techniques for comparing floating point operands often require full processing in a fixed number of stages, consuming power and time, especially in situations where the comparison can be performed more efficiently.
Innovation Solution
A data processing apparatus and method that compares floating point operands in two discrete steps, using first processing logic to evaluate sign, exponent, and most significant bits of the fraction component, and second processing logic only when necessary to determine the comparison result, thereby reducing power consumption and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full floating point comparison is performed in fixed stages, then comparison accuracy is ensured, but power consumption increases and processing time increases
Solution Approach 1:
The comparison operation is divided into two distinct phases: a first phase that compares sign bits, exponent fields, and a limited number of most significant fraction bits to quickly determine the result in most cases, and a second phase that compares remaining fraction bits only when the first phase determines the result is indeterminate. This segmentation allows the system to achieve full comparison accuracy while minimizing power consumption by activating the second phase only when necessary.
Solution Approach 2:
The comparison apparatus dynamically adjusts its operation based on the input operands by using control logic to determine whether the second comparison phase is needed. The system transitions between different operational states: completing the comparison after the first phase when results are determinable, or proceeding to the second phase when indeterminate results require additional fraction bit comparison. This dynamic behavior optimizes power consumption while maintaining accuracy.
2Measurement precision
If full floating point comparison is performed in fixed stages, then comparison accuracy is ensured, but processing time increases
Solution Approach 1:
The comparison operation is divided into two distinct phases: a first phase that compares sign bits, exponent fields, and a limited number of most significant fraction bits to quickly determine the result in most cases, and a second phase that compares remaining fraction bits only when the first phase determines the result is indeterminate. This segmentation allows the system to achieve full comparison accuracy while minimizing processing time by completing most comparisons in the faster first phase.
Solution Approach 2:
The comparison process uses periodic action by executing the first comparison phase in every case, then conditionally executing the second phase only when needed. This periodic execution pattern with conditional continuation optimizes processing time by avoiding unnecessary full comparisons while ensuring accuracy when required.
3Use of energy by moving object
If two-phase comparison is used to reduce power consumption, then power savings are achieved, but device complexity increases
Solution Approach 1:
The comparison apparatus is segmented into distinct functional units: first comparison logic for the initial phase, second comparison logic for the optional second phase, and control logic for managing the transition between phases. This modular segmentation, while increasing component count, organizes complexity in a manageable way that enables power optimization without overwhelming system complexity.
Solution Approach 2:
The control logic performs preliminary evaluation after the first comparison phase to determine whether the second phase is needed before activating it. This preliminary action prevents unnecessary execution of the second phase and its associated logic, thereby reducing the effective complexity experienced during normal operation while maintaining the power-saving benefits of the two-phase architecture.
Data Source
AI summary
A data processing apparatus compares first and second floating point operands to produce a comparison result. For each floating point operand, a first component is derived from a predetermined number of MSBs of the fraction component which is less than the total number of bits constituting the fraction component. The sign and exponent components of the first and second floating point operands are compared to produce a plurality of signals. If possible, the comparison result is determined from the plurality of signals. For each floating point operand, a second component is derived from the bits of the fraction component of that floating point operand other than the predetermined number of MSBs. The second components of the first and second floating point operands to are compared produce a further signal. The comparison result is determined from the plurality of signals and the further signal.