Floating-Point Design Bug Hunting With Targeted Formal Constraints
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic design automation (EDA) tools struggle to conclusively identify bugs in complex floating-point hardware designs, leading to inefficiencies and increased time in bug detection.
Innovation Solution
Implementing automatic formal verification bug hunting techniques that execute multiple concurrent runs with varied constraints to detect hard-to-find bugs in floating-point designs, focusing on input patterns that highlight defects in precision and range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If EDA tools are used for bug detection in floating-point designs, then bug detection capability is provided, but detection accuracy is insufficient and results are inconclusive
Solution Approach 1:
The patent applies preliminary action by pre-processing the floating-point design to identify and extract critical verification points and constraints before formal verification begins. This preparation phase includes analyzing the design structure, identifying potential bug locations, and setting up targeted verification constraints, which enables the subsequent verification to focus on high-risk areas and improve both accuracy and conclusiveness of bug detection
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting verification parameters such as constraint severity levels, analysis depth, and precision thresholds during the verification process. The system modifies these parameters based on intermediate results and design complexity, allowing the verification to adapt its rigor and focus, thereby improving detection accuracy without requiring exhaustive analysis of all design aspects
2Reliability
If formal verification is applied to complex floating-point designs, then bug detection capability is improved, but verification time increases significantly
Solution Approach 1:
The patent applies segmentation by dividing the complex floating-point design into multiple modular segments or modules for independent verification. Each segment is verified separately with tailored constraints, allowing the verification process to proceed in parallel and reducing the overall verification time while maintaining comprehensive coverage of the design
Solution Approach 2:
The patent implements partial action by focusing verification efforts on critical sections of the design where bugs are most likely to occur, rather than performing exhaustive verification of the entire design. The system identifies high-risk areas through static analysis and concentrates formal verification resources on these regions, achieving reliable bug detection with reduced verification time
3Reliability
If comprehensive verification constraints are used, then bug detection coverage is improved, but problem complexity increases
Solution Approach 1:
The patent applies local quality by assigning different constraint types and verification depths to different regions of the design based on their specific characteristics and risk profiles. Critical modules receive more rigorous verification with stricter constraints, while less critical areas use lighter verification, optimizing the balance between coverage and complexity management
Data Source
AI summary
Described herein is a technique for automatic detection of defects via formal verification bug hunting of floating-point designs. In one embodiment the technique specifies a method including loading a hardware definition into an automatic bug fixing tool configured to automatically generate input constraints for formal verification of a device under test (DUT), querying for operational constraints defined for portions of the hardware definition directed towards floating-point operations, adjusting formal verification proofs based on the operational constraints, and performing formal verification of the hardware definition based on adjusted formal verification proofs.