Floating Point Multiply Using Segmented Integer Multipliers
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Solution Overview
Problem
Current processors face challenges in efficiently performing floating-point multiplication operations without requiring specialized, wide-bitwidth floating-point multiplication circuitry, which increases cost, size, and complexity.
Innovation Solution
The processor executes a series of integer multiply instructions and a special-purpose floating-point multiply-accumulate instruction to generate a final floating-point multiplication result, utilizing components sized for smaller bit widths, thereby reducing the need for full-precision multipliers and simplifying routing logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated 64-bit multiplier is included in the processor to perform double-precision floating-point multiplication, then the processor can execute floating-point multiply operations efficiently in a single cycle, but the size, cost, and power consumption of the processor increase
Solution Approach 1:
The patent divides the floating-point multiplication operation into multiple stages using smaller integer multipliers (e.g., two 32-bit multipliers for a 64-bit operation). Instead of using a single large 64-bit multiplier, the significand multiplication is segmented into multiple partial multiplications that are executed sequentially or in parallel using available smaller multipliers, thereby avoiding the need for large dedicated floating-point multiplication circuitry
Solution Approach 2:
The patent makes integer multipliers perform floating-point multiplication operations by treating floating-point significands as integers during the multiplication process. The same integer multiplier hardware is used for both integer multiplication and floating-point multiplication (by extracting and multiplying significands), eliminating the need for separate dedicated floating-point multiplication units and reducing overall processor area
2Productivity
If a dedicated 64-bit multiplier is included in the processor, then floating-point multiplication can be performed in a single cycle, but the processor cost increases
Solution Approach 1:
The patent segments the floating-point multiplication into multiple operations using smaller, cheaper integer multipliers. By breaking down a 64-bit floating-point multiplication into multiple 32-bit (or smaller) integer multiplications, the system uses less expensive hardware components while achieving the same computational result through multiple steps
Solution Approach 2:
The patent uses integer multiplication operations (copies of simpler, well-optimized integer multiply logic) to perform floating-point multiplication. Instead of designing and manufacturing complex dedicated floating-point multiplication circuitry, the system copies and reuses simpler integer multiplier units, reducing manufacturing complexity and cost
3Area of stationary object
If the processor converts a double-precision multiply instruction into a looping operation with multiple partial multiplications, then the processor can use smaller multipliers, but additional complexity and routing logic are introduced into the processor
Solution Approach 1:
The patent merges the integer multiplication and floating-point multiplication functionalities into a unified operation. By combining the exponent addition logic with the significand multiplication (using integer multipliers) and the result assembly into a single integrated floating-point multiply instruction execution path, the patent reduces the need for separate complex routing logic while maintaining the benefit of using smaller multipliers
Data Source
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AI summary
A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.