Floating-Point Norm Instruction Hardware for Parallel Reductions
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Solution Overview
Problem
Existing processing devices face inefficiencies in performing reduction operations, particularly in machine intelligence applications, where large graphs require significant concurrency and parallelism, and existing collective operations like all-reduce collectives are not efficiently handled.
Innovation Solution
A processing device with a hardware module that supports a new type of instruction (norm instruction) for performing two different types of reduction operations in parallel, utilizing a hardware module with accumulators and processing circuits to update state information efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing collective operations like all-reduce collectives are used, then data sharing and processing across multiple processes is enabled, but the efficiency of reduction operations is insufficient for large graphs in machine intelligence applications
Solution Approach 1:
The patent merges multiple reduction operations (e.g., sum and maximum) into a single hardware module that processes both operations simultaneously. This combining of operations within a unified hardware structure enables efficient parallel execution without requiring separate processing paths, thereby improving productivity while managing complexity through integration.
Solution Approach 2:
The hardware module is designed with universal functionality to handle multiple reduction operation types through a single instruction format. The module can perform different reduction operations (sum, maximum, minimum) based on control signals, making it a multi-functional unit that reduces the need for specialized hardware for each operation type, thus improving efficiency without proportionally increasing complexity.
2Loss of time
If multiple reduction operations are performed sequentially, then each operation can be completed accurately, but the overall execution time increases
Solution Approach 1:
The hardware module enables continuous execution of multiple reduction operations in parallel without idle time between operations. By providing dedicated processing circuits that operate simultaneously on different operations, the system maintains continuous productive action, significantly reducing total execution time while preserving accuracy through parallel computation.
Solution Approach 2:
The system performs preliminary initialization of multiple reduction operations in parallel before final computation. By setting up multiple operation instances simultaneously and preparing data structures in advance, the system reduces the time needed for sequential execution while maintaining computational accuracy through proper initialization and synchronization.
3Adaptability or versatility
If separate hardware is provided for each reduction operation, then each operation can be optimized independently, but the hardware complexity and resource consumption increase
Solution Approach 1:
The patent implements a universal hardware module that can perform multiple reduction operations (sum, maximum, minimum, etc.) through a single instruction format and unified processing architecture. This multi-functional design provides adaptability to different reduction operations while avoiding the complexity of separate dedicated hardware for each operation type.
Solution Approach 2:
The hardware module incorporates dynamic control mechanisms that can switch between different reduction operations based on runtime conditions. The processing circuits can be dynamically configured to perform different operations on different data streams, providing flexibility and adaptability without requiring static separate hardware paths for each operation.
4Measurement precision
If reduction operations are performed with high precision, then accurate results are obtained, but the processing speed decreases
Solution Approach 1:
The hardware module maintains continuous high-precision computation through parallel processing circuits that operate simultaneously. By performing multiple precision operations in parallel rather than sequentially, the system achieves both high precision and high speed, as the precision is maintained in each parallel path while the overall throughput is increased through concurrent execution.
Data Source
AI summary
A hardware module is provided in an execution unit and is responsive to execution of multiple instances of a new type of instruction to perform a plurality of reductions in parallel. The hardware module comprises: a first accumulator storing first state associated with a first of the reductions; and a second accumulator storing second state associated with a second of the reductions. Upon execution of each of the multiple instances of the first type of instruction: an input value for the respective instance is provided to a first processing circuit of the hardware module such that the first processing circuit performs a first type of operation to update the first state; and the same input value is provided to the second processing circuit of the hardware module such that the second processing circuit performs a second type of operation to update the second state.