Floating-Point Adder Partitioning for Same-Sign Addition
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Solution Overview
Problem
Existing floating-point addition methods in hardware face a trade-off between power consumption, processing performance, and silicon area, with inefficiencies in adding numbers of mixed signs.
Innovation Solution
Implementing same-sign floating-point adders to combine numbers of the same sign first, followed by mixed-sign adders for the remaining numbers, reducing the need for circuitry that handles different signs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If mixed-sign floating-point adders are used to handle all cases, then versatility is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent divides the floating-point addition task into two separate segments: same-sign addition and mixed-sign addition. Dedicated same-sign adder circuits handle additions where both operands have the same sign, while separate mixed-sign adder circuits handle cases with different signs. This segmentation allows each circuit to be optimized for its specific function, reducing overall complexity compared to a universal adder design.
Solution Approach 2:
The patent extracts the same-sign addition functionality into dedicated circuits that are separate from the mixed-sign addition circuits. By taking out the same-sign case and handling it with specialized hardware, the design reduces the complexity burden on the main addition logic, as same-sign addition requires fewer computational steps and less complex control logic.
2Device complexity
If same-sign adders are used exclusively, then device complexity is reduced, but adaptability to handle mixed-sign numbers deteriorates
Solution Approach 1:
The patent implements a multi-functionality approach by providing both same-sign adder circuits and mixed-sign adder circuits within the same device. The system can adaptively select which type of adder to use based on the input operands' signs, making the overall system universal in handling all floating-point addition cases while keeping individual circuit designs simpler and more specialized.
Solution Approach 2:
The patent introduces dynamic selection logic that determines at runtime whether to route inputs to same-sign or mixed-sign adder circuits based on the sign bits of the operands. This dynamic adaptation allows the system to optimize performance and resource usage for each specific addition operation, maintaining versatility without requiring all circuits to handle all cases.
3Measurement precision
If full-precision floating-point addition circuitry is implemented, then processing precision is improved, but power consumption and silicon area increase
Solution Approach 1:
The patent applies local quality by implementing different precision handling strategies in different parts of the addition circuit based on the input characteristics. For same-sign additions, the circuit can use optimized algorithms that maintain full precision while requiring less complex hardware. For mixed-sign additions, the circuit uses appropriate precision maintenance techniques specific to that case, avoiding the need for all circuit paths to be designed for the most demanding scenario.
Solution Approach 2:
The patent changes operational parameters dynamically based on the input operands. When operands have the same sign, the circuit uses parameter settings optimized for that case (such as different exponent alignment strategies or mantissa handling). When operands have different signs, different parameters are applied. This parameter adaptation maintains precision requirements while reducing the hardware overhead needed for any single fixed configuration.
Data Source
AI summary
Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.