Floating Source Line 2T SONOS Memory Cell Programming
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Solution Overview
Problem
SONOS memory devices face disturbances such as bit line disturb and pass gate disturb, which degrade the reliability of non-volatile memories by causing charge leakage and reducing the separation between programmed and erased threshold voltages, leading to data retention issues and read current errors.
Innovation Solution
The implementation of a floating source line two-transistor (2T) SONOS memory cell configuration, where the source line is connected equipotentially with the bit line during write operations, reduces pass gate disturb by eliminating hot electron injection and bit line disturb by minimizing voltage across memory transistors, thereby maintaining a stable threshold voltage and read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating-gate flash memory is used, then charge storage is achieved, but single point failures occur and programming requires higher voltages
Solution Approach 1:
The patent changes the fundamental parameter of charge storage from conductive gate (floating-gate) to dielectric layer (SONOS), enabling programming at lower voltages while maintaining non-volatility. The SONOS structure uses a charge-trapping dielectric stack between control gate and channel, allowing tunneling at reduced voltage compared to conventional floating-gate devices.
2Reliability
If SONOS transistors are programmed using uniform channel modified Fowler-Nordheim tunneling, then programming reliability is improved, but cell disturbs still interfere with programming
Solution Approach 1:
The patent segments the memory array into blocks and uses block-level programming with selective row activation. By programming one row at a time with controlled word line activation, the patent isolates and prevents disturbs from affecting other cells, thereby reducing cell disturbs while maintaining programming reliability through the segmented approach.
3Reliability
If bit line disturb and pass gate disturb occur, then charge leakage increases and threshold voltage separation decreases, but data retention and read current reliability are degraded
Solution Approach 1:
The patent applies preliminary action by performing block erase operations before programming, and by using selective word line activation to pre-establish clean states. This preliminary preparation prevents charge leakage and threshold voltage shifts during subsequent programming operations, thereby maintaining data retention and reducing read current errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces pass gate and bit line disturbs, enhancing data retention and read current reliability, with reduced threshold voltage shifts and maintained read current over a large number of cycles, thus improving the overall performance and endurance of SONOS memory devices.
Implementation Method 1
A positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer
Implementation Method 2
a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer
Implementation Method 3
SONOS transistors are programmed and erased using a quantum mechanical effect known as uniform channel, modified Fowler-Nordheim tunneling
Data Source
AI summary
Disclosed are a method and device for programming an array of memory cells.