Fluorinated Gate Dielectric Structure for Threshold Voltage Reliability

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Solution Overview

Problem

The existing semiconductor manufacturing processes face challenges in ensuring sufficient fluorine incorporation into gate dielectric layers, leading to inadequate repair of defects and reduced reliability of semiconductor devices, particularly due to fluorine escape during subsequent deposition and etching processes.

Innovation Solution

The method involves performing multiple fluorination treatments at strategic stages of the semiconductor structure formation, specifically after the formation of barrier and work function layers, and after the metal fill layer, to ensure sufficient fluorine incorporation into gate dielectric layers, thereby repairing defects and enhancing the reliability of semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fluorine incorporation is performed once during gate dielectric layer formation, then the process is simple, but fluorine is lost during subsequent deposition and etching processes leading to insufficient defect repair

Engineering Contradiction:
Improvegate dielectric layer qualityVSAvoidnumber of fluorination treatments
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing fluorination treatments at multiple strategic stages before subsequent processes that cause fluorine loss. Specifically, fluorination is performed after gate dielectric layer formation, after barrier layer deposition, and after metal fill layer deposition, ensuring fluorine is replenished before each process that would cause escape, thereby guaranteeing sufficient fluorine incorporation for defect repair.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action by scheduling fluorination treatments at regular intervals throughout the manufacturing process. Instead of a single fluorination event, the process periodically re-incorporates fluorine at three distinct stages, maintaining fluorine concentration in the gate dielectric layer despite continuous loss during subsequent deposition and etching operations.

Inventive Principle:
Principle #19Periodic action

2Reliability

If multiple fluorination treatments are performed, then sufficient fluorine is incorporated into gate dielectric layers, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvesemiconductor device reliabilityVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges fluorination treatments with existing manufacturing stages by performing fluorination after gate dielectric layer formation, after barrier layer deposition, and after metal fill layer deposition. This integration allows fluorine incorporation to be combined with necessary process steps, achieving sufficient defect repair without adding excessive independent process cycles.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively incorporates sufficient fluorine into gate dielectric layers, improving their quality and enhancing the reliability of semiconductor devices by adequately repairing defects, thus addressing the limitations of existing methods.

Implementation Method 1

performing multiple fluorination treatments at strategic stages of the semiconductor structure formation... to ensure sufficient fluorine incorporation into gate dielectric layers

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20240379449A1Semiconductor structure
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379449A1 patent drawing
  • US20240379449A1 patent drawing
  • US20240379449A1 patent drawing

AI summary

A semiconductor structure is provided. The semiconductor structure includes a first n-type transistor having a first threshold voltage and including a first gate dielectric layer, and a second n-type transistor having a second threshold voltage and including a second gate dielectric layer. The first threshold voltage is lower than the second threshold. Each of the first gate dielectric layer and the second gate dielectric layer contains fluorine and hafnium. The first gate dielectric layer has a first average fluorine concentration and a first average hafnium concentration. The second gate dielectric layer has a second average fluorine concentration and a second average hafnium concentration. A first ratio of the first average fluorine concentration to the first average hafnium concentration is greater than and a second ratio of the second average fluorine concentration to the second average hafnium concentration.